Multiplexed distribution system for CMOS signals

• US 6,380,775 B1
• Filed: 06/05/1995
• Issued: 04/30/2002
• Est. Priority Date: 11/30/1993
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Reynolds, David C.
• Primary Examiner(s): Tran, Toan
• Assistant Examiner(s): NGUYEN, LONG T
• Application Number:
  US08/464,298
• Time in Patent Office: 2,521 Days
• Field of Search: 327/261, 327/263, 327/99, 327/198, 327/202, 327/203, 327/211, 327/212, 327/153, 327/161
• US Class Current: 327/153
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: H03K 17/005 with several inputs only
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked outputs of these devices are directed to a multiplexer where the inter-leaved data path signals are recombined into a single output line. This multiplexer includes clocked transmission gates, the clock signals for which are shifted in time by 90° from the clock signals applied to the originating signal sources. The result is that additional time is made available for sampling the digital signals applied to the multiplexer.

Claims

1. A CMOS distribution system with means for efficiently merging two synchronized data signals comprising:

a first clocked CMOS signal source having an output;

first clock means producing first clock pulses and coupled to said first signal source to activate said first signal source at the times of occurrence of said first clock pulses;

a second clocked CMOS signal source and having an output synchronized with the output of said first clocked CMOS signal source;

second clock means producing second clock pulses synchronized with and occurring at times complementary to said first clock pulses;

means coupling said second clock pulses to said second signal source to activate said second signal source at the times of occurrence of said second clock pulses;

first and second transmission gates having inputs and outputs with the inputs coupled to the outputs of said first and second signal sources respectively;

first phase-shifting means coupled to said first clock means to produce third clock pulses phase-shifted by at least approximately 90°

;

means to couple said third clock pulses to said first transmission gate to activate said first gate at the times of occurrence of said third clock pulses;

second phase-shifting means coupled to said second clock means to produce fourth clock pulses phase-shifted by at least approximately 90°

;

means to couple said fourth clock pulses to said second transmission gate to activate said second gate at the times of occurrence of said fourth clock pulses;

means to couple together the outputs of said first and second transmission gates to form a multiplexer for merging the signals produced at the outputs of said first and second transmission gates to develop a stream of signals corresponding to a composite of said synchronized output signals from said first and second clocked CMOS signal sources.

2. The method of distributing digital signals comprising the steps of:

producing first digital signals from a first clocked signal source;

activating said first signal source by a first stream of clock pulses;

producing second signals from a second clocked signal source;

activating said second signal source by a second stream of clock pulses complementary to said first stream of clock pulses;

directing said first digital signals to a first clocked transmission gate;

directing a third stream of clock pulses to said first transmission gate to activate said gate;

said third clock pulses being shifted in phase with respect to said first stream of clock pulses by at least approximately 90°

;

directing said second digital signals to a second clocked transmission gate;

directing a fourth stream of clock pulses to said second transmission gate to activate said second gate;

said fourth clock pulses being shifted in phase with respect to said second stream of clock pulses by at least approximately 90°

;

the phase-shifts of said third and fourth clock pulses being set to provide that said third and fourth clock pulses occur at times intermediate the times of said first and second clock pulses respectively; and

alternatingly merging the signals produced by said first and second transmission gates.