Operational amplifier

• US 6,380,801 B1
• Filed: 06/08/2000
• Issued: 04/30/2002
• Est. Priority Date: 06/08/2000
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: McCartney, Damien
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US09/589,960
• Time in Patent Office: 691 Days
• Field of Search: 330/9, 330/51, 330/136, 330/255, 327/124
• US Class Current: 330/9
• CPC Class Codes: H03F 2203/45462 the CSC comprising a cascode circuit
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 3/3064 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45775 by using cross switches
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

An operational amplifier having two differential input stages. A first one of the stages comprises a pair of first input transistors and another one of such stages comprises a pair of second input transistors. The second input transistors are complementary in type to the first input transistors. A comparator is fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier. The comparator produces a control signal in accordance with a difference between the sense signal and the reference signal. A switching network is responsive to the control signal and couples an output of either the first one of the stages or the second one of the stages to an output of the operational amplifier selectively in accordance with the control signal. An input chop circuit is adapted for coupling to a differential input signal, formed by the non-inverting and inverting input signals, and for providing the differential input signal with a non-inverted polarity during a first time period and such differential input signal with an inverted polarity during a succeeding time period. The differential input signal with the provided inverted polarity and the provided non-inverted polarity are fed to the coupled one of the two stages during the first time period and the succeeding time period, respectively. With such an arrangement, transitional regions where one of the stages that are coupled to the amplifier output is partially operational are eliminated, thereby reducing errors that occur in these transitional regions.

Claims

1. An operational amplifier, comprising:

two differential input stages, a first one of the stages comprising a pair of first input transistors and another one of such stages comprising a pair of second input transistors, such second input transistors being complementary in type to the first input transistors;

a comparator fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier, such comparator producing a control signal in accordance with a difference between the sense signal and the reference signal; and

a switching network, responsive to the control signal, for inhibiting coupling of the first differential input stage to an output of the operational amplifier when the first differential input stage is partially operational and for inhibiting coupling of the second differential input stage to the output of the operational amplifier when the second differential input stage is partially operational.

2. The operational amplifier recited in claim 1 wherein only one of the differential input stages is coupled to the operational amplifier output at a given time.

3. The operational amplifier recited in claim 1 further including a latch fed by the control signal and a strobe signal, for latching the control signal in the latch in response to the strobe signal;

and

wherein the latched control signal is fed to the switching network.

5. The operational amplifier recited in claim 1 where the first input transistors are of type PMOS and where the coupling of the first differential input stage to the operational amplifier output is inhibited when the sense signal is greater than the reference signal.

6. The operational amplifier recited in claim 1 where the second input transistors are of type NMOS and where the coupling of the second differential input stage to the operational amplifier output is inhibited when the sense signal is less than the reference signal.

4. The operational amplifier of claim I where the sense signal is the non-inverting input signal.

7. An operational amplifier, comprising:

two differential input stages, a first one of the stages comprising a pair of first input transistors and another one of such stages comprising a pair of second input transistors, such second input transistors being complementary in type to the first input transistors;

a comparator fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier, such comparator producing a control signal in accordance with a difference between the sense signal and the reference signal; and

a switching network, responsive to the control signal, for coupling either the first or the second differential input stage to an output of the operational amplifier selectively in accordance with the control signal.

8. The operational amplifier recited in claim 7 further including a latch fed by the control signal and a strobe signal, for latching the control signal in the latch in response to the strobe signal;

and

wherein the latched control signal is fed to the switching network.

9. The operational amplifier of claim 7 where the sense signal is the non-inverting input signal.

10. The operational amplifier recited in claim 7 where the first input transistors are of type PMOS and where the first differential input stage is coupled to the operational amplifier output when the sense signal is less than the reference signal.

11. The operational amplifier recited in claim 7 where the second input transistors are of type NMOS and where the second differential input stage is coupled to the operational amplifier output when the sense signal is greater than the reference signal.

12. An operational amplifier, comprising:

two differential input stages, a first one of the stages comprising a pair of first input transistors and another one of such stages comprising a pair of second input transistors, such second input transistors being complementary in type to the first input transistors;

a comparator fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier, such comparator producing a control signal in accordance with a difference between the sense signal and the reference signal;

a switching network, responsive to the control signal, for coupling either the first or the second differential input stage to an output of the operational amplifier selectively in accordance with the control signal; and

an input chop circuit, adapted for coupling to a differential input signal that is formed by the non-inverting and inverting input signals, such chop circuit providing the differential input signal with a non-inverted polarity during a first time period and providing such differential input signal with an inverted polarity during a succeeding time period;

wherein the differential input signal with the provided inverted polarity and the provided non-inverted polarity are fed to the one of the two coupled stages during the first time period and the succeeding time period, respectively.

13. The operational amplifier recited in claim 12 further including a latch fed by the control signal and a strobe signal, for latching the control signal in the latch in response to the strobe signal;

and

wherein the latched control signal is fed to the switching network.

14. The operational amplifier of claim 12 where the sense signal is the non-inverting input signal.

15. The operational amplifier recited in claim 12 wherein the first input transistors are of type PMOS and wherein the first differential input stage is coupled to the operational amplifier when the sense signal is less than the reference signal.

16. The operational amplifier recited in claim 12 wherein the second input transistors are of type NMOS and wherein the second differential input stage is coupled to the operational amplifier when the sense signal is greater than the reference signal.

19. The operational amplifier of claim 12 where the sense signal is the non-inverting input signal.

17. An operational amplifier, comprising:

two differential input stages, a first one of the stages comprising a pair of first input transistors and another one of such stages comprising a pair of second input transistors, such second input transistors being complementary in type to the first input transistors;

two comparators, a first one of the comparators being fed by a sense signal and a first reference signal and a second one of the comparators being fed by the sense signal and a second reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier, such comparators producing first and second control signals in accordance with differences between the sense signal and the first and second reference signals, respectively; and

a switching network, responsive to the control signals, for coupling the first and second differential input stages to an output of the operational amplifier selectively in accordance with the control signals.

18. The operational amplifier recited in claim 17 further including:

a first latch fed by the first control signal and a strobe signal, for latching the first control signal in the latch in response to the strobe signal;

a second latch fed by the second control signal and the strobe signal, for latching the second control signal in the second latch in response to the strobe signal; and

wherein the latched control signals are fed to the switching network.

20. The operational amplifier recited in claim 17 wherein the first input transistors are of type PMOS and wherein the first differential input stage is coupled to the operational amplifier output when the sense signal is less than the first reference signal.

21. The operational amplifier recited in claim 17 wherein the second input transistors are of type NMOS and wherein the second differential input stage is coupled to the operational amplifier output when the sense signal is greater than the second reference signal.