Signal generator, and method

• US 6,380,811 B1
• Filed: 02/16/2001
• Issued: 04/30/2002
• Est. Priority Date: 02/16/2001
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Berman, Konstantin, Zarubinsky, Michael, Zipper, Eliav
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/784,279
• Time in Patent Office: 438 Days
• Field of Search: 331/1.A, 331/16, 331/18, 331/25, 327/156-159, 327/291, 327/299
• US Class Current: 331/18
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0993 and a circuit for adding and deleting pulses
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A signal generator (100) receives an input clock signal (X₁) at a first frequency (F₁) and derives an output clock signal (Y) at a second frequency (F_Y). An arrangement (110) using a first intermediate signal (Z) receives the input clock signal (X₁) and provides a second intermediate signal (X₂) by selectively providing transitions (119) of the second intermediate signal (X₂) at time intervals (T₂(n)) that are determined by a variable number (A+P(n)) of periods (T_Z) of the first intermediate signal (Z). The second intermediate signal (X₂) has a frequency (F₂) that is in average (F′₂) higher than the first frequency (F₁). A phase-looked loop (PLL) circuit (180) locks at this average frequency (F′₂) and provides the output clock signal (Y).

Claims

1. A signal generator that receives an input clock signal at a first frequency and derives an output clock signal at a second frequency, said second frequency being higher than said first frequency, said signal generator comprising:

an arrangement using a first intermediate clock signal, said arrangement receiving said input clock signal and providing a second intermediate clock signal by selectively providing transitions of said second intermediate clock signal at time intervals that are determined by a variable number of periods of said first intermediate clock signal, said second intermediate clock signal having a third frequency with an average higher than said first frequency, said average of said third frequency being related to said first frequency by a first factor; and

a phase-looked loop circuit that locks at said average of said third frequency and provides said output clock signal, said second frequency of said output signal being related to said average of said third frequency of said second intermediate clock signal by a second factor.

2. The signal generator of claim 1 wherein said arrangement comprises a local oscillator that provides said first intermediate clock signal at a fourth frequency higher than said first frequency.

3. The signal generator of claim 2, wherein said fourth frequency is lower than said average of said third frequency.

4. The signal generator of claim 1, wherein said arrangement further comprises:

a phase detector to determine a first representation of the frequency ratio between a fourth frequency of said first intermediate clock signal and said first frequency of said input clock signal;

a filter to filter said first representation to a second representation; and

a divider that provides said transitions of said second intermediate signal depending on said second representation.

5. The signal generator of claim 4, wherein said divider provides said transitions of said second intermediate signals such that said variable number of periods of said first intermediate clock signal, over a period sequence with a number of consecutive periods of said second intermediate clock signal, the average of said variable number being a sum of a first number that is integer and a second number that is real.

6. The signal generator of claim 5, wherein said number of consecutive periods is larger than the frequency ratio between said fourth frequency of said first intermediate clock signal and said first frequency of said input clock signal.

7. The signal generator of claim 4, wherein said first representation is available at time intervals that have substantially equal duration as said period of said input signal.

8. The signal generator of claim 7, wherein said filter samples said first representation at a sampling frequency that is higher than said first frequency.

9. The signal generator of claim 8, wherein said sampling frequency is substantially equal to the frequency of said first intermediate signal.

10. The signal generator of claim 9, wherein said filter samples said first representation with said first intermediate clock signal.

11. The signal generator of claim 4, wherein a feedback unit derives a feedback clock signal from said second intermediate clock signal by counting to said first factor.

12. The signal generator of claim 11, wherein said phase detector determines said first representation by counting periods of said first intermediate signal that occur between predetermined transitions of said input signal and said feedback clock signal.

13. The signal generator of claim 4, wherein said first representation and said second representation are linearly related to the frequency of said first intermediate clock signal.

14. The signal generator of claim 1, wherein said first factor is programmable.

15. The signal generator of claim 1, wherein said first factor is a power-to-2 integer.

16. The signal generator of claim 15, wherein said first factor is selected from the set of 256, 512, and 1024.

17. A method to derive an output clock signal from an input reference clock signal, said method comprising the following steps:

generating a first intermediate clock signal;

providing a second intermediate clock signal by counting periods of said first intermediate clock signal wherein the number of periods of said first intermediate clock signal in said second intermediate clock signal varies and wherein the spectrum of said second intermediate clock signal is being shaped;

decimating said second intermediate clock signal to a feedback clock signal at substantially the same frequency as said input reference clock signal;

calculating a numeric representation of the phase difference between said input reference clock signal and said feedback clock signal by counting periods of said first intermediate clock signal;

using said numeric representation to adjust said number of periods of said first intermediate clock signal in said second intermediate clock signal; and

filtering said second intermediate clock signal to said output signal with a transfer function that is inverse to said spectrum.

18. The method of claim 17, wherein the number of periods of said intermediate clock signal in said intermediate signal varies by quasi random.