Electro-optical devices
First Claim
Patent Images
1. An electro-optical device comprising:
- a first data driver circuit provided over said substrate and comprising at least a first shift register;
a second data driver circuit provided over said substrate and comprising at least a second shift register;
a plurality of data signal odd-numbered lines provided over said substrate and branching out from said first data driver circuit, said data signal odd-numbered lines arranged on odd-numbered columns, respectively;
a plurality of data signal even-numbered lines provided over said substrate and branching out from said second data driver circuit, said data signal even-numbered lines arranged on even-numbered columns, respectively;
at least one pixel thin film transistor provided over said substrate in an active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal odd-numbered lines; and
at least one other pixel thin film transistor provided over said substrate in said active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal even-numbered lines, wherein said data signal odd-numbered lines and said data signal even-numbered lines are arranged alternatively with a line space of 100 μ
m or less between two adjacent lines thereof, and wherein first video signals for pixels arranged on a row are processed into second video signals shortened to half time length of said first video signals, wherein said second video signals are distributed to said data signal odd-numbered lines through said first shift register, wherein third video signals having an inverted waveform of said second video signals and having an opposite polarity to said second video signals are distributed to said data signal even-numbered lines through said second shift register, and wherein a select signal output from a last stage of said first shift register is entered to a first stage of said second shift register to conduct a line inversion in which said third video signals have the opposite polarity to said second video signals.
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Abstract
In a display device comprising a plurality of pixels arranged in matrix form, there are provided two or more row driving and/or column driving circuits aligned parallel to each other. This arrangement serves to reduce intervals between rows and/or columns driven by each of the parallel driving circuits so that the pixels of the matrix can be arranged at a higher density. With this parallel arrangement of the driving circuits, interlaced scanning as well as line inversion and dot inversion of video signals are simplified and the operating frequency of the driving circuits can be reduced.
59 Citations
12 Claims
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1. An electro-optical device comprising:
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a first data driver circuit provided over said substrate and comprising at least a first shift register;
a second data driver circuit provided over said substrate and comprising at least a second shift register;
a plurality of data signal odd-numbered lines provided over said substrate and branching out from said first data driver circuit, said data signal odd-numbered lines arranged on odd-numbered columns, respectively;
a plurality of data signal even-numbered lines provided over said substrate and branching out from said second data driver circuit, said data signal even-numbered lines arranged on even-numbered columns, respectively;
at least one pixel thin film transistor provided over said substrate in an active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal odd-numbered lines; and
at least one other pixel thin film transistor provided over said substrate in said active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal even-numbered lines, wherein said data signal odd-numbered lines and said data signal even-numbered lines are arranged alternatively with a line space of 100 μ
m or less between two adjacent lines thereof, andwherein first video signals for pixels arranged on a row are processed into second video signals shortened to half time length of said first video signals, wherein said second video signals are distributed to said data signal odd-numbered lines through said first shift register, wherein third video signals having an inverted waveform of said second video signals and having an opposite polarity to said second video signals are distributed to said data signal even-numbered lines through said second shift register, and wherein a select signal output from a last stage of said first shift register is entered to a first stage of said second shift register to conduct a line inversion in which said third video signals have the opposite polarity to said second video signals. - View Dependent Claims (2, 3)
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4. A semiconductor device comprising:
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a substrate;
a first data driving circuit provided over said substrate and comprising at least a first shift register;
a second data driving circuit provided over said substrate and comprising at least a second shift register;
a plurality of data signal odd-numbered lines provided over said substrate and branching out from said first data driver circuit, said data signal odd-numbered lines arranged on odd-numbered columns, respectively;
a plurality of data signal even-numbered lines provided over said substrate and branching out from said second data driver circuit, said data signal even-numbered lines arranged on even-numbered columns, respectively;
at least one pixel thin film transistor provided over said substrate in an active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal odd-numbered lines; and
at least one other pixel thin film transistor provided over said substrate in said active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal even-numbered lines, wherein first video signals for pixels arranged on a row are processed into second video signals shortened to half time length of said first video signals, wherein said second video signals are distributed to said data signal odd-numbered lines through said first shift register, wherein third video signals having an inverted waveform of said second video signals and having an opposite polarity to said second video signals are distributed to said data signal even-numbered lines through said second shift register, and wherein a select signal output from a last stage of said first shift register is entered to a first stage of said second shift register to conduct a line inversion in which said third video signals have the opposite polarity to said second video signals. - View Dependent Claims (5, 6)
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7. A semiconductor device comprising:
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a substrate;
a first data driving circuit provided over said substrate and comprising at least a first shift register;
a second data driving circuit provided over said substrate and comprising at least a second shift register;
a plurality of data signal odd-numbered lines provided over said substrate and branching out from said first data driver circuit, said data signal odd-numbered lines arranged on odd-numbered columns, respectively;
a plurality of data signal even-numbered lines provided over said substrate and branching out from said second data driver circuit, said data signal even-numbered lines arranged on even-numbered columns, respectively;
at least one pixel thin film transistor provided over said substrate in an active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal odd-numbered lines; and
at least one other pixel thin film transistor provided over said substrate in said active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal even-numbered lines; and
a gate line provided over said substrate, wherein first video signals for pixels arranged on a row are processed into second video signals shortened to half time length of said first video signals, wherein said second video signals are distributed to said data signal odd-numbered lines through said first shift register, wherein third video signals having an inverted waveform of said second video signals and having an opposite polarity to said second video signals are distributed to said data signal even-numbered lines through said second shift register, and wherein a select signal output from a last stage of said first shift register is entered to a first stage of said second shift register to conduct a line inversion in which said third video signals have the opposite polarity to said second video signals. - View Dependent Claims (8, 9)
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10. A semiconductor device comprising:
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a substrate;
a first data driving circuit provided over said substrate and comprising at least a first shift register;
a second data driving circuit provided over said substrate and comprising at least a second shift register;
a plurality of data signal odd-numbered lines provided over said substrate and branching out from said first data driver circuit, said data signal odd-numbered lines arranged on odd-numbered columns, respectively;
a plurality of data signal even-numbered lines provided over said substrate and branching out from said second data driver circuit, said data signal even-numbered lines arranged on even-numbered columns, respectively;
at least one pixel thin film transistor provided over said substrate in an active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal odd-numbered lines; and
at least one other pixel thin film transistor provided over said substrate in said active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal even-numbered lines, wherein first video signals for pixels arranged on a row are processed into second video signals shortened to half time length of said first video signals, wherein said second video signals are distributed to said data signal odd-numbered lines through said first shift register, wherein third video signals having an inverted waveform of said second video signals and having an opposite polarity to said second video signals are distributed to said data signal even-numbered lines through said second shift register, wherein a select signal output from a last stage of said first shift register is entered to a first stage of said second shift register to conduct a line inversion in which said third video signals have the opposite polarity to said second video signals, and wherein said active matrix is scanned in an interlace manner.
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11. A semiconductor device comprising:
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a substrate;
a first data driving circuit provided over said substrate and comprising at least a first shift register;
a second data driving circuit provided over said substrate and comprising at least a second shift register;
a plurality of data signal odd-numbered lines provided over said substrate and branching out from said first data driver circuit, said data signal odd-numbered lines arranged on odd-numbered columns, respectively;
a plurality of data signal even-numbered lines provided over said substrate and branching out from said second data driver circuit, said data signal even-numbered lines arranged on even-numbered columns, respectively;
at least one pixel thin film transistor provided over said substrate in an active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal odd-numbered lines; and
at least one other pixel thin film transistor provided over said substrate in said active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal even-numbered lines, wherein first video signals for pixels arranged on a row are processed into second video signals shortened to half time length of said first video signals, wherein said second video signals are distributed to said data signal odd-numbered lines through said first shift register, wherein third video signals having an inverted waveform of said second video signals and having an opposite polarity to said second video signals are distributed to said data signal even-numbered lines through said second shift register, wherein a select signal output from a last stage of said first shift register is entered to a first stage of said second shift register to conduct a line inversion in which said third video signals have the opposite polarity to said second video signals, and wherein said active matrix is scanned in a non-interlace manner.
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12. A semiconductor device comprising:
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a substrate;
a first data driving circuit provided over said substrate and comprising at least a first shift register;
a second data driving circuit provided over said substrate and comprising at least a second shift register;
a plurality of data signal odd-numbered lines provided over said substrate and branching out from said first data driver circuit, said data signal odd-numbered lines arranged on odd-numbered columns, respectively;
a plurality of data signal even-numbered lines provided over said substrate and branching out from said second data driver circuit, said data signal even-numbered lines arranged on even-numbered columns, respectively;
at least one pixel thin film transistor provided over said substrate in an active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal odd-numbered lines; and
at least one other pixel thin film transistor provided over said substrate in said active matrix and having a source region and a drain region one of which is connected to a corresponding one of said data signal even-numbered lines, wherein first video signals for pixels arranged on a row are processed into second video signals shortened to half time length of said first video signals, wherein said second video signals are distributed to said data signal odd-numbered lines through said first shift register, wherein third video signals having an inverted waveform of said second video signals and having an opposite polarity to said second video signals are distributed to said data signal even-numbered lines through said second shift register, wherein a select signal output from a last stage of said first shift register is entered to a first stage of said second shift register to conduct a line inversion in which said third video signals have the opposite polarity to said second video signals, and wherein said first data driving circuit is provided on opposite side of said active matrix to said second data driving circuit.
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Specification