Test system with signal injection network for characterizing interference and noise tolerance in a digital signal link

• US 6,381,269 B1
• Filed: 05/28/1999
• Issued: 04/30/2002
• Est. Priority Date: 05/28/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Steinberger, Michael L., Gradl, David A.
• Primary Examiner(s): CORRIELUS, JEAN B
• Application Number:
  US09/322,827
• Time in Patent Office: 1,068 Days
• Field of Search: 375/224, 375/227, 375/254, 375/285, 375/340, 714/46, 714/48, 714/712, 714/714, 714/715, 714/724, 714/738, 714/739, 324/512, 324/520, 324/521, 324/527, 324/528, 324/674, 324/681, 324/603, 324/628, 324/722
• US Class Current: 375/224
• CPC Class Codes: H04B 3/46 Monitoring; Testing

Abstract

A test system for a evaluating a digital signal link includes a data signal generator, a data signal receiver, a digital signal link to be tested and a test interference signal injection (TISI) network connected as part of the digital signal link. The TISI network includes a data signal input port for receiving digital data signals generated by the data signal generator, a data signal output port for providing the digital data signals to the data signal receiver, and a controlled impedance data signal path carrying the digital data signals between the data signal input port and the data signal output port. An interference signal input port receives interference signals over a range of frequencies from an interference signal generator. One or more directional couplers directionally couple the interference signals into the data signal path toward either the data signal output port or the data signal input port at an impedance that substantially matches the impedance of the digital signal link. The directional couplers are configured to maintain d.c. isolation from ground to facilitate the transfer of d.c. coupled data signal logic through the TISI network.

Claims

1. A test system for characterizing interference tolerance in a digital signal link, comprising:

a digital data signal generator;

a digital data signal receiver;

a digital signal link connected between said data signal generator and said data signal receiver and carrying digital data signals generated by said data signal generator to said data signal receiver;

a test interference signal injection (TISI) network disposed in said digital signal link;

a data signal input to said TISI network for receiving said digital data signals from said digital signal link;

a data signal output from said TISI network for returning said digital data signals to said digital signal link;

an interference signal input to said TISI network for receiving interference signals from an interference signal generator; and

directional coupling means in said TISI network for directionally coupling said interference signals into said digital signal link at an impedance that substantially matches the impedance of said digital signal link, said directional coupling means being configured to maintain d.c. isolation from ground to facilitate the transfer of d.c. coupled logic in said digital data signals through said TISI network.

2. A test system in accordance with claim 1 wherein said directional coupling means includes one or more broadband directional coupling transformers.

3. A test system in accordance with claim 2 wherein the ground connections of said directional coupling transformers are connected to a plurality of parallel bypass capacitors to provide a floating node that acts as an a.c. ground, and which allows said d.c. coupled logic in said digital data signals to pass through said directional coupling transformers to said data signal output.

4. A test system in accordance with claim 3 further including a series capacitor disposed between said interference signal input and each of said directional coupling transformers for blocking d.c. voltage levels in said interference signals.

5. A test system in accordance with claim 2 wherein there are two of said directional coupling transformers adapted for coupling common mode interference signals and differential mode interference signals into said digital signal link.

6. A test system in accordance with claim 5 further including phase splitter means for receiving said interference signals from said interference signal input port and selectively providing said interference signals to said directional couplers as a pair of same-phase common mode interference signals or a pair of opposite-phase differential mode interference signals.

7. A test system in accordance with claim 6 wherein said phase splitter means includes a pair of impedance matching transformers, including a non-phase splitting grounded end terminal transformer for producing said pair of said same-phase common mode interference signals and a phase splitting, grounded center-tapped transformer for producing said pair of opposite-phase differential mode interference signals.

8. A test system in accordance with claim 7 wherein said phase splitter means further includes a switch-activated radio frequency relay for selectively routing said common mode interference signals and said differential mode interference signals from said impedance matching transformers to said directional coupling transformers.

9. A test system in accordance with claim 1 further including one or more monitoring ports for connecting signal monitoring equipment to one or more locations on said digital signal link for monitoring said digital data signals carried thereon.

10. A test system for characterizing interference tolerance in a pair of first and second high speed digital signal links connected to a unit under test (UUT) and adapted for carrying either common mode serial data signals or differential mode serial data signals, said test system comprising:

a data signal generating and analysis suite containing a data signal generator and a data signal receiver;

a test board mounting a driver end of said first digital signal link and a receiver end of said second digital signal link;

a UUT having a receiver end circuit and a driver end circuit, and being capable of operating in a loopback mode wherein digital signals received at said receiver end circuit are directed to said driver end circuit while bypassing other signal processing components of said UUT;

a first link segment cable forming part of said first digital signal link and extending from said test board to said UUT receiver end circuit;

a second link segment cable forming part of said second digital signal link and extending from said UUT driver end circuit to said test board;

said data signal generator being connected to provide digital data signals to said driver end of said first digital signal link;

said data signal receiver being connected to receive digital data signals from said receiver end of said second digital signal link;

a test interference signal injection (TISI) network mounted on said test board and connected as part of either said first digital signal link or said second digital signal link;

a serial data signal input port in said TISI network for receiving said high speed serial data signals generated by said data signal generator;

a serial data signal output port in said TISI network for providing said high speed serial data signals to said digital data signal receiver;

a controlled impedance, high speed serial data path in said TISI network carrying said high speed serial data signals from said data signal input port to said data signal output port;

an interference signal input port in said TISI network for receiving interference signals from an interference signal generator;

a phase splitter in said TISI network adapted to receive said interference signals from said interference signal port and to selectively provide common mode interference signals or differential mode interference signals; and

a pair of directional couplers in said TISI network adapted to selectively couple said common mode interference signals or said differential mode interference signals into said high speed serial data path, the ground connections of said directional couplers being connected to a floating node providing an a.c.- bypassing/d.c.- isolated ground that allows normal d.c. voltage levels of said high speed serial data signals to pass through said directional couplers to either said data signal output port or said data signal input port.

11. A test system in accordance with claim 10 wherein said TISI network is connected in said first digital signal link between said first digital signal link driver end and said first link segment cable.

12. A test system in accordance with claim 10 wherein said TISI network is configured for selectable connection in either said first digital signal link between said first digital signal link driver end and said first link segment cable or said second digital signal link between said second link segment cable and said second digital signal link receiver end.

13. A test system in accordance with claim 10 wherein said data signal generator includes a pattern generator circuit, a pattern generator clock circuit and a logic analyzer circuit.

14. A test system in accordance with claim 13 wherein said pattern generator and logic analyzer circuits respectively transmit and receive parallel, positive emitter coupled logic (PECL) signals to and from said test board, wherein said digital signal links carry serial, low voltage differential signals (LVDS) to and from said UUT, and wherein said test board further includes serial-to-parallel and parallel-to-serial signal conversion circuits and PECL-to-LVDS and LVDS-to-PECL signal translation circuits, for transitioning between said parallel PECL signals carried by said pattern generator and logic analyzer circuits and said serial LVDS signals carried by said digital signal links.

15. A test system in accordance with claim 14 further including a clock recovery circuit for deriving clock signals from said serial LVDS signals received at said second digital signal link receiver end.

16. A test system in accordance with claim 15 further including a frame detector circuit for framing said parallel PECL signals prior to passing said signals to said logic analyzer circuit.

17. A test system in accordance with claim 16 wherein said directional couplers comprise broadband directional coupling transformers, and wherein said transformer ground pins are connected through an array of bypass capacitors to the test system ground to provide said a.c.- bypassing/d.c.-isolated ground.

18. A test system in accordance with claim 17 wherein said bypass capacitor array includes a plurality of parallel-connected capacitors of different values for bypassing different a.c. frequencies to ground.

19. A test system in accordance with claim 18 wherein said directional couplers are adapted to couple said interference signals into said data signal path over a bandwidth of at least about 300 MHz.

20. A test system for characterizing interference tolerance in a digital signal link, comprising:

a digital data signal generator for generating high speed serial data signals;

a digital data signal receiver for receiving said high speed serial data signals;

a digital signal link connected to carry said serial data signals generated by said data signal generator to said data signal receiver;

a test interference signal injection (TISI) network connected as part of said digital signal link;

a data signal input port in said TISI network for receiving said high speed serial data signals generated by said data signal generator;

a data signal output port in said TISI network for providing said high speed serial data signals to said data signal receiver;

a controlled impedance data signal path in said TISI network carrying said high speed serial data signals between said data signal input port and said data signal output port;

an interference signal input port in said TISI network for receiving interference signals over a range of frequencies from an interference signal generator;

phase splitter means in said TISI network for receiving said interference signals and selectively providing common mode interference signals and differential mode interference signals for injection into said data signal path, said phase splitter means including a pair of impedance matching transformers, including a non-phase splitting grounded end terminal transformer for providing a pair of same-phase common mode interference signals and a phase splitting grounded center-tap terminal transformer for providing a pair of opposite-phase differential mode interference signals, said phase splitter means further including a switch-activated radio frequency relay for selecting between said common mode interference signals and said differential mode interference signals;

directional coupling means in said TISI network for receiving said interference signals from said phase splitter means and including two broadband directional coupling transformers for selectively coupling said common mode interference signals or said differential mode interference signals into said data signal path, said interference signals being coupled toward either said data signal output port or said data signal input port at an impedance that substantially matches the impedance of said digital signal link, said directional coupling means being configured to maintain d.c. isolation from ground by connecting the ground pins of said directional coupling transformers to a plurality of parallel bypass capacitors to provide a floating node that acts as an a.c. ground and which allows d.c. voltage levels in said high speed serial data signals to pass through said test interference signal injection network; and

one or more monitoring ports in said digital signal link for connecting signal monitoring equipment thereto in order to monitor said high speed serial data signals carried thereon.