ETSI intelligent network capability set 1 intelligent network application protocol service switching point finite state machine

• US 6,381,328 B1
• Filed: 04/07/1998
• Issued: 04/30/2002
• Est. Priority Date: 08/29/1997
• Status: Expired due to Term

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Morton, Edward, Polsley, Patricia Diane, Tsioras, Constantine Nicholas
• Primary Examiner(s): Matar, Ahmad F.
• Assistant Examiner(s): BUI, BING Q
• Application Number:
  US09/056,402
• Time in Patent Office: 1,484 Days
• Field of Search: 379/88.2, 379/127, 379/156, 379/201, 379/221.08, 379/221.09, 379/221.12, 379/229, 326/37, 326/46, 709/227, 709/230, 370/352, 710/105, 712/220, 712/232
• US Class Current: 379/221.08
• CPC Class Codes: H04Q 3/0037 involving call modelling techniques, e.g. modifications to the basic call state model [BCSM]

Abstract

A finite state machine that implements the ETSI Intelligent Network Capability Set 1 for INAP protocol using a first finite state machine connected to a second finite state machine. To accomplish this implementation, the first finite state machine receives inputs and makes initial state transition choices. Once the first finite state machine has made an initial choice, the second finite state machine checks to see if the first finite state machine has transitioned to the appropriate state and, if it has not, give feedback to the finite state machine to the appropriate state. Once the appropriate state is reached, the outputs of the first finite state machine are valid and available. The finite state machines may be realized as physical logical devices or virtually using VFSM technology.

Claims

1. A hierarchical finite state machine that provides integrated control of an input condition of an input register subsequent to determining a state of an output register, the hierarchical finite state machine comprising a first finite state machine (410) including said input register, characterized by:

the first state machine (410) having a common register (level 6 of 410, level 1 of 440) having a state which depends on the input condition of said input register;

a second finite state machine (440) connected to said first finite state machine (410), the common register comprising outcome results of the first state machine and serving as an input to the second finite state machine (440);

the second finite state machine (440) determining the state of the output register (Send) following the first finite state machine determining the outcome result of the common register; and

the second finite state machine changing the input condition of said input register of the first state machine if the state of the common register is validated by a predetermined set of rules (levels 2,3 of 440) implemented by the second finite state machine (440), thereby readying the first state machine (410) to process new information consistent with a previously determined state of the output register (Send).

2. The finite state machine of claim 1, further comprising:

said first and second finite state machine each being a virtual finite state machine implemented with VFSM technology; and

a processor for sequencing said virtual finite state machines.

3. The finite state machine of claim 1, wherein:

said first and second finite state machines implement ETSI INAP capability set 1 intelligent network application protocol.

4. The finite state machine of claim 1, wherein the states in the first finite state machine are cohesive and are de-coupled from the other states.

5. A method for providing integrated control of an input condition of an input register subsequent to determining a state of an output register in a hierarchical finite state machine, the method including the step of utilizing an input register of a first finite state machine (410), the method characterized by the steps of:

sharing the state of a common register (level 6 of 410, level 1 of 440) between the first state machine (410) and the second state machine (440), the state of the common register depending on the input condition of said input register;

the common register containing outcome results as determined by the first state machine and serving as an input to the second finite state machine (440);

following the first finite state machine determining the outcome result of the common register, the second finite state machine (440) determining the state of the output register (Send); and

changing, by the second finite state machine, the input condition of said input register of the first state machine if the state of the common register is validated by a predetermined set of rules (levels 2,3 of 440) implemented by the second finite state machine (440), thereby readying the first state machine (410) to process new information consistent with a previously determined state of the output register (Send).

6. The method of claim 5 further comprising implementing said first and second finite state machine each by a virtual finite state machine implemented with VFSM technology;

and using a processor for sequencing said virtual finite state machines.

7. The method of claim 5 wherein said first and second finite state machines implement ETSI INAP capability set 1 intelligent network application protocol.

8. The method of claim 5 wherein the states in the first finite state machine are cohesive and are de-coupled from the other states.