Queued port data controller for microprocessor-based engine control applications

• US 6,381,532 B1
• Filed: 09/20/2000
• Issued: 04/30/2002
• Est. Priority Date: 09/20/2000
• Status: Expired due to Fees

• Current Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Original Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Inventors: Guido, Samuel J., Anderson, Robert L., Stevens, Raymond A., Gravenstein, Martin G., Fisher, Rollie M., Rishavy, Kevin M., Bastian, Gary T.
• Primary Examiner(s): Dolinar, Andrew M.
• Application Number:
  US09/665,094
• Time in Patent Office: 587 Days
• Field of Search: 701/114, 701/115, 710/8-10, 710/15-19
• US Class Current: 701/114
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

Claims

1. A queued port rate register (QRR) system supporting a host processor, said QRR system comprising:

a plurality of peripheral devices, each of said peripheral devices having a first memory unit having a first and second transaction register for storing communication parameters for each of said corresponding plurality of peripheral devices;

a second memory unit in operative communication with said plurality of peripheral devices for storing data for transmission to said plurality of peripheral devices in accordance with said first and second transaction registers; and

a peripheral counter in operative communication with each of said plurality of peripheral devices, said peripheral counter adapted to interrogate each of said plurality of peripheral devices and, when data has been written to one of said peripheral devices, update said peripheral device according to said second memory unit data.

2. The QRR system according to claim 1 wherein said first transaction register comprises a delay-after-transmit (DAT) field, a Baud field, and a Concatenate field.

3. The QRR system according to claim 1 wherein said second transaction register comprises a delay-before-transmit (DBT) field, a Data Bit field, and a Peripheral Chip Select field.

4. The QRR system according to claim 1 further comprising an address multiplexor in operative communication between said second memory unit and said peripheral counter for receiving said first and second transaction register communication parameters and pointing to a corresponding location in said second memory unit to enable said data transmission.

5. The QRR system according to claim 4 further comprising a queued port submodule (QSPM) in operative communication with each of said plurality of peripheral devices for initializing each of said first and second transaction registers associated with each of said plurality of peripheral devices.

6. An engine control system comprising:

a host processor in operative communication with a data bus;

a plurality of peripheral devices for communicating engine operating parameters, each of said peripheral devices having a first and second transaction register for storing communication parameters for each of said corresponding plurality of peripheral devices; and

,

a queued port rate register (QRR) including a memory unit in operative communication with said plurality of peripheral devices for storing data for transmission to said plurality of peripheral devices in accordance with said first and second transaction registers; and

a peripheral counter in operative communication with each of said plurality of peripheral devices, said peripheral counter adapted to interrogate each of said plurality of peripheral devices and, when data has been written to one of said peripheral devices, update said peripheral device according to said memory unit data.

7. The engine control system of claim 6 wherein said first transaction register comprises a delay-after-transmit (DAT) field, a Baud field, and a Concatenate field.

8. The engine control system of claim 6 wherein said second transaction register comprises a delay-before-transmit (DBT) field, a Data Bit field, and a Peripheral Chip Select field.

9. The engine control system of claim 6 further comprising an address multiplexor in operative communication between said memory unit and said peripheral counter for receiving said first and second transaction register communication parameters and pointing to a corresponding location in said memory unit to enable said data transmission.

10. The engine control system of claim 9 further comprising a queued port submodule (QSPM) in operative communication with each of said plurality of peripheral devices for initializing each of said first and second transaction registers associated with each of said plurality of peripheral devices.

11. The engine control system of claim 6 wherein said peripheral counter is adapted to serially interrogate each of said peripheral devices.

12. A method of controlling data flow in an engine control system comprising a host processor, a plurality of peripheral data devices, each of said peripheral data devices having a first and second transaction register for storing communication parameters, and a queue control unit including associated memory having a first portion for storing queue control commands associated with each peripheral device and a second portion for storing peripheral device data, the method comprising the steps of:

receiving an event trigger indicative of a desired data transfer between said host processor and at least one selected peripheral device;

loading a queue control command into said queue control unit from said first memory portion associated with said selected peripheral device;

transmitting all data associated with said selected peripheral device to said host processor;

detecting an interrupt event;

storing said peripheral device data of said second portion associated with said selected peripheral device; and

servicing said interrupt event.

13. The method of claim 12 wherein said step of detecting an interrupt event includes the step of detecting an interrupt event from another peripheral device, and said step of servicing said interrupt event includes transmitting all data associated with said interrupting peripheral device to said host processor.

14. The method of claim 13 further comprising the step of, after servicing said interrupt event, restoring said stored peripheral device data of said second portion associated with said selected peripheral device.