Apparatus and method to precisely position packets for a queue based memory controller
First Claim
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1. An apparatus comprising:
- a timestamp logic circuit in communication with a queue based memory controller having a queue with a plurality of queue positions, the timestamp logic circuit designating scheduled times for each queue position, some of the queue positions having a packet scheduled at a scheduled time by the memory controller; and
a plurality of bubble adders utilized with the timestamp logic circuit to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet;
wherein the timestamp logic circuit comprises a plurality of chained timestamp logic units, the chained timestamp logic units including a plurality of standard timestamp logic units and a first timestamp logic unit, each standard timestamp logic unit corresponding to a queue position and each standard timestamp logic unit designating a scheduled time for the respective queue position, the first timestamp logic unit corresponding to the first queue position and designating the scheduled time for the first queue position.
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Abstract
Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.
13 Citations
16 Claims
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1. An apparatus comprising:
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a timestamp logic circuit in communication with a queue based memory controller having a queue with a plurality of queue positions, the timestamp logic circuit designating scheduled times for each queue position, some of the queue positions having a packet scheduled at a scheduled time by the memory controller; and
a plurality of bubble adders utilized with the timestamp logic circuit to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet;
wherein the timestamp logic circuit comprises a plurality of chained timestamp logic units, the chained timestamp logic units including a plurality of standard timestamp logic units and a first timestamp logic unit, each standard timestamp logic unit corresponding to a queue position and each standard timestamp logic unit designating a scheduled time for the respective queue position, the first timestamp logic unit corresponding to the first queue position and designating the scheduled time for the first queue position. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory subsystem comprising:
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a queue based memory controller having a queue with a plurality of queue positions;
a memory channel coupled to the queue based memory controller;
a plurality of memory devices coupled to the memory channel;
a timestamp logic circuit coupled to the queue based memory controller, the timestamp logic circuit designating scheduled times for each queue position, some of the queue positions having a packet scheduled at a scheduled time by the memory controller, the packet being transmitted onto the memory channel at a scheduled time to perform an action on a memory device; and
a plurality of bubble adders utilized with the timestamp logic circuit to add bubbles to queue positions to precisely position the scheduled time at which the packet is transmitted to the memory bus;
wherein the timestamp logic circuit comprises a plurality of chained timestamp logic units, the chained timestamp logic units including a plurality of standard timestamp logic units and a first timestamp logic unit, each standard timestamp logic unit corresponding to a queue position and each standard timestamp logic unit designating a scheduled time for the respective queue position, the first timestamp logic unit corresponding to the first queue position and designating the scheduled time for the first queue position. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification