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Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation

  • US 6,381,670 B1
  • Filed: 03/25/1997
  • Issued: 04/30/2002
  • Est. Priority Date: 01/07/1997
  • Status: Expired due to Term
First Claim
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1. A flash memory, which provides adjustable bias conditions for erase and program operations, comprising:

  • a memory array having an array of memory cells arranged in rows and columns for storing desired memory data, whereby each row of memory cells is connected by a word line and each column of memory cells is connected by bit lines;

    a lookup table storing adjustable bias conditions including control gate voltage Vc, source voltage Vs, drain voltage Vd, pulse width and pulse number;

    a counter register connected to to said lookup table to control settings of the adjustable bias conditions;

    a counter connected to said counter register to receive a starting value from said counter register and to control contents said counter register;

    a verify voltage generator connected to said counter register for generating verify voltages according to said control value;

    a program voltage generator connected to said lookup table for generating program voltages necessary to place the desired memory data within said memory array, according to the adjustable bias conditions from said lookup table;

    an erase voltage generator connected to said lookup table for generating erase voltages necessary to remove memory data from said memory array, according to the adjustable bias conditions from said lookup table;

    an address register for receiving and storing the memory address of at least one of the memory cells in said memory array which is to have memory data programmed or erased;

    a scanning and decoding circuit connected to the verify voltage generator, the program voltage generator, the erase voltage generator, and the address register to accept said verify voltages, said program voltages, said erase voltages, and the memory address for erasing and programming at least one of the memory cells, said scanning and decoding circuit including;

    a scanning circuit for detecting which word line connected to one row of memory cells has been selected for erasing or programming;

    a column decoder for determining from said memory address which desired column of memory cells has been selected for erasing or programming; and

    a row decoder for flexibly selecting at least one word line connected to one row of the memory cells to be erased or programmed and disabling the word lines of rows of nonselected memory cells, wherein said scanning and decoding circuit is controlled to detect maximum and minimum threshold voltages of the memory cells on a row of memory cells for determining an optimal bias condition prior to an erase or program operation;

    a column selector connected to said scanning and decoder circuit and to said memory array for selecting the desired columns of said memory array;

    a sense amplifier connected to said column selector for detecting the desired memory data read from said memory array, said sense amplifier having a control line connected to said counter for stopping said counter to determine said maximum threshold voltages of the memory cells on a row of memory cells;

    a data-in register connected to said column selector for storing the desired memory data to be programmed in said memory array;

    an input/output buffer connected to said sense amplifier and said data-in register for buffering the desired memory data to stored in and read from said memory array;

    a state machine connected to said counter register, said counter, and said lookup table for controlling the erase and program operations of said memory array;

    and a command register connected to the state machine for storing commands and controlling said state machine.

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