Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation

• US 6,381,670 B1
• Filed: 03/25/1997
• Issued: 04/30/2002
• Est. Priority Date: 01/07/1997
• Status: Expired due to Term

• Current Assignee: Secure Axcess LLC (Prism Technologies Group, Inc.)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Tsao, Hsing-Ya, Hsu, Fu-Chang, Fan, Wen-Tan
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/823,571
• Time in Patent Office: 1,862 Days
• Field of Search: 365/94, 365/103, 365/104, 711/103, 711/102
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.

Claims

1. A flash memory, which provides adjustable bias conditions for erase and program operations, comprising:

a memory array having an array of memory cells arranged in rows and columns for storing desired memory data, whereby each row of memory cells is connected by a word line and each column of memory cells is connected by bit lines;

a lookup table storing adjustable bias conditions including control gate voltage Vc, source voltage Vs, drain voltage Vd, pulse width and pulse number;

a counter register connected to to said lookup table to control settings of the adjustable bias conditions;

a counter connected to said counter register to receive a starting value from said counter register and to control contents said counter register;

a verify voltage generator connected to said counter register for generating verify voltages according to said control value;

a program voltage generator connected to said lookup table for generating program voltages necessary to place the desired memory data within said memory array, according to the adjustable bias conditions from said lookup table;

an erase voltage generator connected to said lookup table for generating erase voltages necessary to remove memory data from said memory array, according to the adjustable bias conditions from said lookup table;

an address register for receiving and storing the memory address of at least one of the memory cells in said memory array which is to have memory data programmed or erased;

a scanning and decoding circuit connected to the verify voltage generator, the program voltage generator, the erase voltage generator, and the address register to accept said verify voltages, said program voltages, said erase voltages, and the memory address for erasing and programming at least one of the memory cells, said scanning and decoding circuit including;

a scanning circuit for detecting which word line connected to one row of memory cells has been selected for erasing or programming;

a column decoder for determining from said memory address which desired column of memory cells has been selected for erasing or programming; and

a row decoder for flexibly selecting at least one word line connected to one row of the memory cells to be erased or programmed and disabling the word lines of rows of nonselected memory cells,

wherein said scanning and decoding circuit is controlled to detect maximum and minimum threshold voltages of the memory cells on a row of memory cells for determining an optimal bias condition prior to an erase or program operation;

a column selector connected to said scanning and decoder circuit and to said memory array for selecting the desired columns of said memory array;

a sense amplifier connected to said column selector for detecting the desired memory data read from said memory array, said sense amplifier having a control line connected to said counter for stopping said counter to determine said maximum threshold voltages of the memory cells on a row of memory cells;

a data-in register connected to said column selector for storing the desired memory data to be programmed in said memory array;

an input/output buffer connected to said sense amplifier and said data-in register for buffering the desired memory data to stored in and read from said memory array;

a state machine connected to said counter register, said counter, and said lookup table for controlling the erase and program operations of said memory array;

and a command register connected to the state machine for storing commands and controlling said state machine.

2. The flash memory as claimed in claim 1, wherein said scanning and decoding circuit applies a control gate voltage Vc and a source voltage Vs provided by said erase voltage generator according to said adjustable bias conditions stored in said lookup table for erasing memory cells, and said row decoder providing a first voltage to the word lines which are selected but already successfully erased, a second voltage to the word lines which are selected and still to be erased, and a third voltage to unselected word lines simultaneously for executing a sequential verify operation for the erased memory cells.

3. The flash memory as claimed in claim 2, wherein said sequential verify operation comprises the step of applying a verify voltage to a word line connected to a row of erased memory cells to validate if the threshold voltage of an erased memory cell on the row of erased memory cells has achieved an erased state voltage level.

4. The flash memory as claimed in claim 2, wherein said sequential verify operation comprises the step of applying an increasing voltage to a word line of erased memory cells to turn on all erased memory cells on the word line and terminate said verify operation, said increasing voltage being increased from a first negative voltage to a maximum threshold voltage at which all erased memory cells on the word line are turned on.

5. The flash memory as claimed in claim 2, wherein said sequential verify operation comprises the step of applying a decreasing voltage to a word line of erased memory cells to just turn off at least one erased memory cell on the row of memory cells and terminate said verify operation, said decreasing voltage being decreased from a high voltage to a maximum threshold voltage at which at least one erased memory cell on the row of memory cells is just turned off.

6. The flash memory as claimed in claim 2, wherein said adjustable bias conditions for said control gate voltage Vc and said source voltage Vs are determined by threshold voltages of memory cells selected for erasing to reduce hole trapping.

7. The flash memory as claimed in claim 6, wherein said adjustable bias conditions for said control gate voltage Vc and said source voltage Vs are determined by the maximum threshold voltage of said memory cells selected for erasing.

8. The flash memory as claimed in claim 1, wherein said scanning and decoding circuit programs memory cells selected for programming bit line by bit line with the adjustable bias conditions and executes a sequential verify operation by programming all the selected memory cells to a desired threshold voltage below the threshold voltage for data “

0” and

then programming the selected memory cells to their desired threshold voltages according to desired memory data stored in the data-in register.

9. The flash memory as claimed in claim 8, wherein said adjustable bias conditions depend on the minimum threshold voltage of said memory cells selected for programming.

10. The flash memory as claimed in claim 8, wherein said adjustable bias conditions for programming all the selected memory cells to a desired threshold voltage below the threshold voltage for data “

0”

is achieved by applying incrementally and repetitively a programming voltage from approximately −

5 V to approximately 0 V to the word lines connected to the rows of selected memory cells whereby each programming voltage is incrementally modified by approximately 1 V.

11. The flash memory as claimed in claim 8, wherein said scanning and decoding circuit programs selected memory cells in groups dependent on the detected maximum and minimum threshold voltage of said selected memory cells.

12. The flash memory as claimed in claim 8, wherein said sequential verify operation further comprises the step of applying a voltage to a word line of a row of programmed memory cells to validate if the threshold voltage of the selected memory cells on the word line reaches a desired value for a program state.

13. The flash memory as claimed in claim 2, wherein a location of said memory cells to be selected to be erased is decoded from the memory address retained in the address register and said row decoder comprises a plurality of word line latches for storing a selection state for each row of said memory cells selected for erasing, whereby the selection state has a first condition wherein the row of memory cells is successfully erased and a second condition wherein the row of memory cells is still to be erased.

14. The flash memory as claimed in claim 13, wherein said row decoder further comprises a block latch for storing the state of selection for a block of the plurality of word line latches and indicating that the block of the plurality of word line latches is selected if at least one word line connected to the block of the plurality of word line latches is selected.

15. The flash memory as claimed in claim 1, wherein said row decoder erases memory cells selected for erasing by applying the control gate voltage Vc and the source voltage Vs provided by said erase voltage generator according to said adjustable bias conditions stored in said lookup table, said control gate voltage Vc ranging from a most negative value to a least negative value and said source voltage Vs ranging from a least positive value to a most positive value, said control gate voltage Vc being gradually adjusted from its least negative value to its most negative value by setting source voltage Vs at its least positive value for executing an iterative erase operation initially and said source voltage Vs being gradually adjusted from its least positive value to its most positive value by setting control gate voltage Vc at its most negative value for executing further erase operation.

16. The flash memory as claimed in claim 1, wherein said scanning circuit comprises a serial type scanning means for scanning a plurality of memory banks sequentially, each of said memory banks comprising a plurality of memory blocks and each memory block comprising a plurality of rows of memory cells.

17. The flash memory as claimed in claim 1, wherein said scanning circuit comprises a parallel type scanning for scanning a plurality of memory banks in parallel, each of said memory banks comprising a plurality of memory blocks and each memory block comprising a plurality of rows of memory cells.

18. The flash memory as claimed in claim 1, wherein said verify voltage generator further comprises a test input providing a test mode in which the threshold voltage of a memory cell is measured by applying an externally controlled voltage to the word line connected to the row of the memory cell being measured.

19. An erase/program method for fully eliminating over-erasure of a non-volatile memory including a plurality of memory cells arranged in an array of rows and columns for retaining memory data, whereby each row of memory cells is connected by a word line and each column of memory cells is connected by bit lines, whereby a plurality of rows form a memory block and a plurality of memory blocks form a memory bank, and wherein said erase/program method is comprising the steps of:

selecting at least one word line connected to a row of memory cells to be erased;

detecting a maximum threshold voltage level and a minimum threshold voltage level of the selected memory cells connected to the selected word line;

executing an erase operation for erasing memory cells of at least one row of memory cells connected to the word lines selected for erasing to a low state with an adjustable bias condition to maintain low vertical and horizontal electric fields in the memory cells for decreasing hole trapping and stabilizing threshold voltages of said memory cells, said memory cells having lower threshold voltages in a low state, said bias condition being optimally determined by the maximum and minimum threshold voltages of the memory cells connected to the row of memory cells which are connected to said selected word lines;

performing an erase-verify operation for erase-verifying memory cells erased in said erase operation by applying an erase-verify voltage to the word lines connected to the rows of memory cells being erase-verified and applying a disable voltage to word lines connected to rows of memory cells being erased-verified;

selecting at least one word line connected to a row of memory cells to be programmed;

executing a program operation for programming selected memory cells to a high state with an adjustable bias condition to achieve a maximum gate injection current for speeding up program operation, said selected memory cells having higher threshold voltages in a high state; and

performing a program-verify operation for program-verifying selected memory cells programmed in said program operation by applying a program-verify voltage to the word lines connected to rows of selected memory cells being program-verified and applying a disable voltage to word lines connected to rows of memory cells being program-verified.

20. The erase/program method as claimed in claim 19, wherein said disable voltage in said erase-verify operation is lower than a minimum threshold voltage determined by the detecting of the minimum threshold voltage of said memory cells of the rows of memory cells connected to the selected word lines after said erase operation with a serial scanning means, said serial scanning means having word line latches attached to each word line indicating an erasure state of the row of memory cells connected to each word line, block latches connected to each memory block indicating the erasure state of said memory block whereby said serial scanning means scans the block latches and the word line latches of each memory bank to identify erase memory cells.

21. The erase/program method as claimed in claim 19, wherein said program operation further comprises the step of programming over-erased cells having threshold voltages lower than approximately 0 V bit line by bit line, said programming has the steps of:

detecting the threshold voltages of the selected memory cells;

ordering a location of the selected memory cells according to their threshold voltages; and

reiteratively programming the selected cells starting with those selected memory cells having a lowest threshold.

22. The erase/program method as claimed in claim 19, wherein said program operation further comprises the step of programming selected memory cells with data “

0” and

data “

1”

according to the contents of a data-in register.

23. The erase/program method as claimed in claim 19, wherein said erase operation comprises the step of deeply erasing all selected memory cells to an over-erased state, and said program operation of comprises the step of programming all selected memory cells to data “

0”

.

24. The erase/program method as claimed in claim 19, wherein said adjustable bias conditions for erase and program operations respectively are retained in a lookup table and chosen according to the detected maximum and minimum threshold voltages.

25. The erase/program method as claimed in claim 19, wherein said disable voltage in said erase-verify operation is lower than a minimum threshold voltage determined by the detecting of the minimum threshold voltage of said memory cells of the rows of memory cells connected to the selected word lines after said erase operation with a parallel scanning means, said parallel scanning means having word line latches attached to each word line indicating an erasure state of the row of memory cells connected to each word line, block latches connected to each memory block indicating the erasure state of said memory block whereby said parallel scanning means scans the block latches and the word line latches of each memory bank to identify erase memory cells.

26. The flash memory as claimed in claim 19, wherein said scanning and decoding circuit applies a control gate voltage Vc and a source voltage Vs provided by said erase voltage generator according to said adjustable bias conditions stored in said lookup table for erasing memory cells, and said row decoder providing a first voltage to the word lines which are selected but already successfully erased, a second voltage to the word lines which are selected and still to be erased and a third voltage to unselected word lines simultaneously for executing a sequential verify operation for the erased memory cells.

27. The flash memory as claimed in claim 26, wherein said sequential verify operation comprises the step of applying a verify voltage to a word line connected to a row of erased memory cells to validate if the threshold voltage of an erased memory cell on the row of erased memory cells has achieved an erased state voltage level.

28. The flash memory as claimed in claim 26, wherein said sequential verify operation comprises the step of applying an increasing voltage to a word line of erased memory cells to turn on all erased memory cells on the word line and terminate said verify operation, said increasing voltage being increased from a first negative voltage to a maximum threshold voltage at which all erased memory cells on the word line are turned on.

29. The flash memory as claimed in claim 26, wherein said sequential verify operation comprises the step of applying a decreasing voltage to a word line of erased memory cells to just turn off at least one erased memory cell on the row of memory cells and terminate said verify operation, said decreasing voltage being decreased from a high voltage to a maximum threshold voltage at which at least one erased memory cell on the row of memory cells is just turned off.

30. The flash memory as claimed in claim 26, wherein said adjustable bias conditions for said control gate voltage Vc and said source voltage Vs are determined by threshold voltages of memory cells selected for erasing to reduce hole trapping.

31. The flash memory as claimed in claim 30, wherein said adjustable bias conditions for said control gate voltage Vc and said source voltage Vs are determined by the maximum threshold voltage of said memory cells selected for erasing.

32. The flash memory as claimed in claim 26, wherein a location of said memory cells to be selected to be erased is decoded from the memory address retained in the address register and said row decoder comprises a plurality of word line latches for storing a selection state for each row of said memory cells selected for erasing, whereby the selection state has a first condition wherein the row of memory cells is successfully erased and a second condition wherein the row of memory cells is still to be erased.

33. The flash memory as claimed in claim 32, wherein said row decoder further comprises a block latch for storing the state of selection for a block of the plurality of word line latches and indicating that the block of the plurality of word line latches is selected if at least one word line connected to the block of the plurality of word line latches is selected.

34. A flash memory, which provides adjustable bias conditions for erase and program operations, comprising:

a memory array having an array of memory cells arranged in rows and columns for storing desired memory data, whereby each row of memory cells is connected by a word line and each column of memory cells is connected by bit lines;

a lookup table storing adjustable bias conditions including control gate voltage Vc, source voltage Vs, drain voltage Vd, pulse width and pulse number;

a counter register connected to said lookup table to control settings of the adjustable bias conditions;

a verify voltage generator connected to said counter register for generating verify voltages according to said control value;

an analog to digital converter connected to the verify voltage generator, the counter register, and the lookup table, for converting verify voltages to digital values and sending said digital values to said counter register and said lookup table;

a program voltage generator connected to said lookup table for generating program voltages necessary to place the desired memory data within said memory array, according to the adjustable bias conditions from said lookup table;

an erase voltage generator connected to said lookup table for generating erase voltages necessary to remove memory data from said memory array, according to the adjustable bias conditions from said lookup table;

an address register for receiving and storing the memory address of at least one of the memory cells in said memory array which is to have memory data programmed or erased;

a scanning and decoding circuit connected to the verify voltage generator, the program voltage generator, the erase voltage generator, and the address register to accept said verify voltages, said program voltages, said erase voltages, and the memory address for erasing and programming at least one of the memory cells, said scanning and decoding circuit including;

a scanning circuit for detecting which word line connected to one row of memory cells has been selected for erasing or programming;

a column decoder for determining from said memory address which desired column of memory cells has been selected for erasing or programming; and

a row decoder for flexibly selecting at least one word line connected to one row of the memory cells to be erased or programmed and disabling the word lines of rows of nonselected memory cells,

wherein said scanning and decoding circuit is controlled to detect maximum and minimum threshold voltages of the memory cells on a row of memory cells for determining an optimal bias condition prior to an erase or program operation;

a column selector connected to said scanning and decoder circuit and to said memory array for selecting the desired columns of said memory array;

a sense amplifier connected to said column selector for detecting the desired memory data read from said memory array, said sense amplifier having a control line connected to said counter for stopping said counter to determine said maximum threshold voltages of the memory cells on a row of memory cells;

a data-in register connected to said column selector for storing the desired memory data to be programmed in said memory array;

an input/output buffer connected to said sense amplifier and said data-in register for buffering the desired memory data to stored in and read from said memory array;

a state machine connected to said counter register, said counter and said lookup table for controlling the erase and program operations of said memory array;

and a command register connected to the state machine for storing commands and controlling said state machine.

35. The flash memory as claimed in claim 34, wherein said scanning and decoding circuit programs memory cells selected for programming bit line by bit line with the adjustable bias conditions and executes a sequential verify operation by programming all the selected memory cells to a desired threshold voltage below the threshold voltage for data “

0” and

then programming the selected memory cells to their desired threshold voltages according to desired memory data stored in the data-in register.

36. The flash memory as claimed in claim 35, wherein said adjustable bias conditions depend on the minimum threshold voltage of said memory cells selected for programming.

37. The flash memory as claimed in claim 35, wherein said adjustable bias conditions for programming all the selected memory cells to a desired threshold voltage below the threshold voltage for data “

0”

is achieved by applying incrementally and repetitively a programming voltage from approximately −

5 V to approximately 0 V to the word lines connected to the rows of selected memory cells whereby each programming voltage is incrementally modified by approximately 1 V.

38. The flash memory as claimed in claim 35, wherein said scanning and decoding circuit programs selected memory cells in groups dependent on the detected maximum and minimum threshold voltage of said selected memory cells.

39. The flash memory as claimed in claim 35, wherein said sequential verify operation further comprises the step of applying a voltage to a word line of a row of programmed memory cells to validate if the threshold voltage of the selected memory cells on the word line reaches a desired value for a program state.

40. The flash memory as claimed in claim 34, wherein said row decoder erases memory cells selected for erasing by applying the control gate voltage Vc and the source voltage Vs provided by said erase voltage generator according to said adjustable bias conditions stored in said lookup table, said control gate voltage Vc ranging from a most negative value to a least negative value and said source voltage Vs ranging from a least positive value to a most positive value, said control gate voltage Vc being gradually adjusted from its least negative value to its most negative value by setting source voltage Vs at its least positive value for executing an iterative erase operation initially and said source voltage Vs being gradually adjusted from its least positive value to its most positive value by setting control gate voltage Vc at its most negative value for executing further erase operation.

41. The flash memory as claimed in claim 34, wherein said scanning circuit comprises a serial type scanning means for scanning a plurality of memory banks sequentially, each of said memory banks comprising a plurality of memory blocks and each memory block comprising a plurality of rows of memory cells.

42. The flash memory as claimed in claim 34, wherein said scanning circuit comprises a parallel type scanning means for scanning a plurality of memory banks in parallel, each of said memory banks comprising a plurality of memory blocks and each memory block comprising a plurality of rows of memory cells.

43. The flash memory as claimed in claim 34, wherein said verify voltage generator further comprises a test input providing a test mode in which the threshold voltage of a memory cell is measured by applying an externally controlled voltage to the word line connected to the row of the memory cell being measured.