Parallel processor comprising multiple sub-banks to which access requests are bypassed from a request queue when corresponding page faults are generated

• US 6,381,686 B1
• Filed: 01/12/1999
• Issued: 04/30/2002
• Est. Priority Date: 01/16/1998
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Imamura, Yoshihiko
• Primary Examiner(s): An, Meng-Al T.
• Assistant Examiner(s): LIN, WEN TAI
• Application Number:
  US09/228,653
• Time in Patent Office: 1,204 Days
• Field of Search: 710/240, 710/128, 711/157, 711/119, 711/5, 711/6, 711/117, 711/203, 711/129, 712/245, 712/228, 712/234, 712/28, 712/203
• US Class Current: 711/203
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/253 Centralized memory

Abstract

A parallel processor capable of exhibiting a high processing performance, which when receiving as input access requests generating page faults to sub-banks from a plurality of processor elements connected to a common bus and another access request is input while data is being transferred between sub banks and an external memory via an external access bus in response to the input access requests, a shared memory stores the other access request in a request queue and makes a control circuit execute the stored access request when the stored access request does not generate a page fault.

Claims

1. A parallel processor comprising:

a plurality of processor elements, each including an internal memory storing one or more sub-pages and performing using data stored in the internal memory;

a first data bus connected to the plurality of processor elements;

a second data bus connected in an external memory; and

a shared memory connected to both the first and second buses;

the shared memory including;

a storage means having a plurality of sub-banks storing the sub-pages,

a control means for controlling data transfer between the internal memory of the processor elements and the storage means through the first bus and data transfer between the storage means and the external memory through the second bus, and

an access request management means for receiving as input an access request which generates a page fault to the storage means from the processor elements, storing another access request when another access request is input during the data transfer due to the access request between the shared memory and the external memory through the second bus, and causing the control means to execute the stored other access request when the stored other access request does not generate a page fault.

2. A parallel processor according to claim 1, wherein the access request management means enables storage of a plurality of access requests and makes the control means execute an access request among the plurality of stored access requests which does not generate a page fault when a plurality of access requests are stored prior to a stored access request generating a page fault.

3. A parallel processor according to claim 1, wherein the access management means makes the control means execute access requests in order of storage among the stored plurality of access requests which do not generate a page fault when a plurality of access requests which do not generate a page fault are stored.

4. A parallel processor according to claim 1, wherein the access management means stores the plurality of access requests by a queue method.

5. A parallel processor according to claim 1, further comprising a selecting means for connecting the plurality of sub-banks to the first bus and the second bus.

6. A parallel processor according to claim 1, wherein the control means performs parallel processing for transfer of a sub-page between the storage means and a processor element and for transfer of a sub-page between the storage means shared memory and the external memory when the sub-page to be transferred between the storage means of the shared memory and the processor element and the sub-page which is to be transferred between the storage means and the external memory differ.

7. A parallel processor according to claim 1, wherein a data transfer rate of the first bus is equal to or faster than the data transfer rate of the second bus.

8. A parallel processor according to claim 1, wherein each sub-bank of a storage region of the storage means has a single data port.

9. A parallel processor according to claim 1, wherein the control means stores the plurality of sub-pages comprising a same page in different sub-banks.

10. A parallel processor according to claim 1, wherein the plurality of sub-banks of the storage means have the same memory capacity.

11. A parallel processor according to claim 1, wherein the number of the sub-banks of the storage means is equal to the number of the sub-banks forming a page.

12. A parallel processor according to claim 1, wherein a processor element has a plurality of sub-banks, each storing a single sub-page.

13. A parallel processor according to claim 1, wherein the plurality of sub-pages comprising a page have continuous addresses in an address domain of the external memory.

14. A parallel processor according to claim 1, wherein the data of a sub-page is image data, and

the plurality of processor elements carry out image processing using the image data.

21. A parallel processor according to claim 1, wherein the control means controls data transfer between the storage means of the shared memory and the external memory in page units.

15. A processing method including the steps of:

storing one or more sub-pages in a shared memory having storage regions comprising a plurality of sub-banks, each having a single data port and accessed by a plurality of processor elements;

controlling transfer between the internal memory of the processor elements and the shared memory through a first data bus and data transfer between the shared memory and an external memory through a second data bus in response to an access request from a processor element; and

when a processor element issues an access request accompanied with a page fault to the shared memory and during the transfer of data between the shared memory and external memory through the second bus in response to that access request another processor element issues and access request, storing the access request issued by the other processor element, judging if the stored access request causes a page fault or not, and, when judging that it does not cause a page fault, executing the stored access request.

16. A processing method according to claim 15, said method executing a plurality of stored access requests not causing page faults before a previously stored access request accompanied with the page fault when a plurality of access requests are stored.

17. A processing method according to claim 15, said method executing a plurality of stored access requests which do not cause a page fault in the order of storage when a plurality of access requests which do not cause a page fault are stored.

18. A processing method according to claim 15, said method storing the plurality of access requests by a queue method.

19. A processing method according to claim 15, said method performing control for parallel processing for transfer of a sub-page between the shared memory and a processor element and for transfer of a sub-page between the shared memory and the external memory when the sub-page to be transferred between the shared memory and the processor element and the sub-page which is to be transferred between the shared memory and the external memory differ.

20. A processing method according to claim 15, wherein a data transfer rate of the first bus is equal to or higher than the data transfer rate of the second bus.