Flexible memory channel

• US 6,381,687 B2
• Filed: 02/18/1999
• Issued: 04/30/2002
• Est. Priority Date: 12/23/1998
• Status: Expired due to Term

• Current Assignee: Axis AB (Canon Inc.)
• Original Assignee: Axis AB (Canon Inc.)
• Inventors: Sandström, Stefan, Lundberg, Stefan
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/252,173
• Publication Number:
  US 20020019905A1
• Time in Patent Office: 1,167 Days
• Field of Search: 711/217, 711/218, 711/219, 711/213, 711/131, 711/140
• US Class Current: 711/213
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A memory channel means transferring data streams between different blocks and an internal memory means on a data chip, wherein said memory channel means comprises several memory channels. Each channel has source and destination data stream interfaces, wherein each interface is connectable to different blocks, and a flexible address generator generating source and destination addresses for the internal memory means, wherein the order of the data being transferred is changed.

Claims

1. A chip for data processing, comprising:

at least one interface for receipt of an input data stream;

a plurality of data processing blocks each independently performing an associated data processing function on data derived from the input data stream and providing output data corresponding thereto;

internal memory means for intermediate storage of data in various stages of processing;

a plurality of memory channels, each controllable to provide configurable data transfer paths for concurrent transfer of data between selected ones of the plurality of data processing blocks via the internal memory means; and

a CPU for controlling the plurality of memory channels to effect the pipelined processing of the data derived from the input data stream from the at least one interface among the plurality of data processing blocks.

2. The chip for data processing of claim 1, with the at least one interface for receipt of image input data and wherein the plurality of data processing blocks comprise:

a discrete cosine transform block (DCT) for transformation of the image input data into DCT coefficients;

a quantizer for quantizing the coefficients of the DCT; and

an encoder for variable length coding of the quantized coefficients.

3. The chip for data processing of claim 1, wherein the plurality of memory channels each comprise:

interfaces for coupling to a selected source within one of internal memory means and the plurality of data processing blocks and a selected destination within an other of the plurality of internal memory means and the plurality of data processing blocks.

4. The chip for data processing of claim 3, wherein the plurality of memory channels each further comprise:

a programmable address generator for changing an order of the data transferred.

5. The chip for data processing of claim 3, wherein the plurality of memory channels each further comprise:

a programmable address generator for changing an order of the data transferred and including;

a first counter for each channel adapted to be decremented for each data unit transferred;

a second counter adapted to be decremented after the last decrement and before reload of the first counter; and

an address calculator for adding a first stride value to a current source or destination address for each decrement of the first counter and a second stride value to the current source or destination address for each decrement of the second counter.

6. The chip for data processing of claim 5, wherein the address generator is adapted to reload said first counter and said second counter with predetermined values after their last decrements.

7. The chip for data processing of claim 3, wherein the address generator further comprises:

a data unit counter to count a number of received data units.

8. The chip for data processing of claim 3, wherein each memory channel further comprises:

a memory channel status register to indicate whether a transfer has been completed, not been initiated, or is in progress.

9. The chip for data processing of claim 3, wherein each memory channel further comprises:

a source/destination selection register for indication of whether the channel is operating in source or destination mode.

10. A method for establishing memory channels for transferring data streams between a plurality of data processing blocks and an internal memory means on a data chip, and the method comprising for each memory channel the acts of:

decrementing a first counter for each data unit transferred;

adding a first stride value to a current source or destination address for each decrement of the first counter;

decrementing a second counter after the last decrement and before reload of the first counter; and

adding a second stride value to said current source or destination address for each decrement of the second counter.

11. The method for establishing memory channels of claim 10, further comprising the act of:

reloading the first counter and the second counter predetermined values after their respective last decrements.

12. The method for establishing memory channels of claim 10, further comprising the act of:

counting the number of received data units from a source interface of each of the memory channels.

13. The method for establishing memory channels of claim 10, further comprising the act of:

storing a status value indicating whether a transfer has been completed, not been initiated, or is in progress for each channel.