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Flexible memory channel

  • US 6,381,687 B2
  • Filed: 02/18/1999
  • Issued: 04/30/2002
  • Est. Priority Date: 12/23/1998
  • Status: Expired due to Term
First Claim
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1. A chip for data processing, comprising:

  • at least one interface for receipt of an input data stream;

    a plurality of data processing blocks each independently performing an associated data processing function on data derived from the input data stream and providing output data corresponding thereto;

    internal memory means for intermediate storage of data in various stages of processing;

    a plurality of memory channels, each controllable to provide configurable data transfer paths for concurrent transfer of data between selected ones of the plurality of data processing blocks via the internal memory means; and

    a CPU for controlling the plurality of memory channels to effect the pipelined processing of the data derived from the input data stream from the at least one interface among the plurality of data processing blocks.

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