Serial port for a hose adapter integrated circuit using a single terminal

• US 6,381,688 B1
• Filed: 05/25/2000
• Issued: 04/30/2002
• Est. Priority Date: 11/09/1994
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Burns, Christopher, Gates, Stillman F.
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US09/579,863
• Time in Patent Office: 705 Days
• Field of Search: 709/201, 709/208, 709/236, 709/248, 710/101-106, 710/126, 712/32, 712/38, 713/1
• US Class Current: 712/32
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit. The serial port pin in the host adapter integrated circuit is connected to a shifter circuit in the serial port that serially clocks data from the serial port pin and passes the data parallelly to a bus in the host adapter integrated circuit and vice versa.

Claims

1. An apparatus comprising:

a first integrated circuit having a first serial port wherein said first serial port has only a first bidirectional pin;

wherein said first serial port further comprises a line controller circuit coupled to said first bi-directional pin;

wherein said line controller circuit transfers a command packet serially to said first bi-directional pin;

further wherein said line controller circuit receives an acknowledge packet serially from said first bi-directional pin;

wherein said line controller circuit further comprises a drive line;

wherein said line controller circuit transfers said command packet to said first bidirectional pin in response to an active signal on said drive line; and

further wherein said line controller circuit receives said acknowledgment packet from said first bidirectional pin only in response to an inactive signal on said drive line;

a second integrated circuit having a second serial port wherein said second serial port has only a second bidirectional pin;

a serial port input-output line connecting said first bidirectional pin to said second bidirectional pin, said serial port input-output line being a bidirectional line;

wherein said second integrated circuit generates a second signal on said second bidirectional pin in response to a first signal from said first integrated circuit on said first bidirectional pin;

wherein one of said first and second integrated circuits waits for a signal from the other of said first and second integrated circuits.

2. The apparatus of claim 1 wherein:

said line controller circuit comprises (i) an input buffer coupled to said first bidirectional pin and (ii) an output driver coupled to said first bidirectional pin and to said drive line;

wherein an active signal on said drive line enables said output driver to pass said command packet to said first bidirectional pin; and

further wherein an inactive signal on said drive line disables said output driver to allow said input buffer to receive said acknowledgment packet from said first bidirectional pin.

3. The apparatus of claim 2, wherein:

said output driver in said line controller circuit comprises at least one logic element, said logic element selectively passing said command packet to said first bidirectional pin in dependence on said signal on said drive line.

6. The apparatus of claim 1 wherein the duration of wait is a predetermined time period of at least two cycles in a clock signal.

7. The apparatus of claim 1 wherein the first integrated circuit further comprises:

a first plurality of pins couplable to a first bus;

a second plurality of pins couplable to a second bus; and

a data transfer circuit connected to said first and second pluralities of pins;

wherein said data transfer circuit transfers information between said first plurality of pins and said second pluralities of pins; and

wherein said first bus is an input and output bus connected to a peripheral device and said second bus is a system bus connected to a host processor.

8. The apparatus of claim 7 wherein:

said system bus is coupled to said first serial port; and

said first serial port further comprises a command generator circuit having a serial port input-output bus coupled to said system bus, and a parallel output bus wherein in response to a signal on said serial input-output bus, said command generator circuit drives a command signal on said parallel bus.

4. The apparatus of clam 1 wherein said first serial port further comprises:

a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and

said serial port alternately stores in said plurality of storage elements an input signal received from said bidirectional pin and an output signal to be transmitted on said bidirectional pin.

5. The apparatus of claim 4 wherein said first integrated circuit further comprises:

a processor data bus; and

a processor address bus;

wherein said plurality of storage elements are coupled to said processor data bus and said processor address bus so that a processor coupled to said processor data bus and to said processor address bus can load data into said plurality of storage elements.

9. An apparatus comprising:

a first integrated circuit having a first serial port wherein said first serial port has only a first bidirectional pin;

a second integrated circuit having a second serial port wherein said second serial port has only a second bidirectional pin;

a serial port input-output line connecting said first bidirectional pin to said second bidirectional pin, said serial port input-output line being a bidirectional line;

wherein said second integrated circuit generates a second signal on said second bidirectional pin in response to a first signal from said first integrated circuit on said first bidirectional pin;

wherein said second integrated circuit waits for a predetermined time period after receipt of said first signal before transmission of said second signal,

wherein said first integrated circuit also waits for said predetermined time period to become sensitive to an active signal on said serial port input-output line.

10. An apparatus comprising:

a first integrated circuit having a first serial port wherein said first serial port has only a first bidirectional pin;

a second integrated circuit having a second serial port wherein said second serial port has only a second bidirectional pin;

a serial port input-output line connecting said first bidirectional pin to said second bidirectional pin, said serial port input-output line being a bidirectional line;

wherein said second integrated circuit generates a second signal on said second bidirectional pin in response to a first signal from said first integrated circuit on said first bidirectional pin;

wherein said second integrated circuit waits for a predetermined time period after receipt of said first signal before transmission of said second signal;

wherein said first serial port further comprises;

a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and

said serial port alternately stores in said plurality of storage elements an input signal received from said bidirectional pin and an output signal to be transmitted on said bidirectional pin.

11. The apparatus of claim 10 wherein said first integrated circuit further comprises:

a processor data bus; and

a processor address bus;

wherein said plurality of storage elements are coupled to said processor data bus and said processor address bus so that a processor coupled to said processor data bus and to said processor address bus can load data into said plurality of storage elements.

12. An apparatus comprising:

a first integrated circuit having a first serial port wherein said first serial port has only a first bidirectional pin;

a second integrated circuit having a second serial port wherein said second serial port has only a second bidirectional pin;

a serial port input-output line connecting said first bidirectional pin to said second bidirectional pin, said serial port input-output line being a bidirectional line;

wherein said second integrated circuit generates a second signal on said second bidirectional pin in response to a first signal from said first integrated circuit on said first bidirectional pin;

wherein said second integrated circuit waits for a predetermined time period after receipt of said first signal before transmission of said second signal; and

wherein the duration of said predetermined time period is at least two cycles in a clock signal.

13. An apparatus comprising:

first integrated circuit having a first serial port wherein said first serial port has only a first bidirectional pin;

a second integrated circuit having a second serial port wherein said second serial port has only a second bidirectional pin;

a serial port input-output line connecting said first bidirectional pin to said second bidirectional pin, said serial port input-output line being a bidirectional line;

wherein said second integrated circuit generates a second signal on said second bidirectional pin in response to a first signal from said first integrated circuit on said fist bidirectional pin;

wherein said second integrated circuit waits for a predetermined time period after receipt of said first signal before transmission of said second signal; and

wherein the first integrated circuit further comprises;

a first plurality of pins couplable to a first bus;

a second plurality of pins couplable to a second bus; and

a data transfer circuit connected to said first and second pluralities of pins;

wherein said data transfer circuit transfers information between said first plurality of pins and said second pluralities of pins; and

wherein said first bus is an input and output bus connected to a peripheral device and said second bus is a system bus connected to a host processor.

14. The apparatus of claim 13 wherein:

said system bus is coupled to said first serial port; and

said first serial port further comprises a command generator circuit having a serial port input-output bus coupled to said system bus, and a parallel output bus wherein in response to a signal on said serial input-output bus, said command generator circuit drives a command signal on said parallel bus.

15. An apparatus comprising:

a first integrated circuit having a first serial port wherein said first serial port has only a first bidirectional pin;

a second integrated circuit having a second serial port wherein said second serial port has only a second bidirectional pin;

a serial port input-output line connecting said first bidirectional pin to said second bidirectional pin, said serial port input-output line being a bidirectional line;

wherein said second integrated circuit generates a second signal on said second bidirectional pin in response to a first signal from said first integrated circuit on said first bidirectional pin;

wherein said first integrated circuit waits for a predetermined time period after receipt of said second signal before transmission of another first signal.

16. The apparatus of claim 15, wherein said first serial port further comprises:

a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements, and said serial port alternately stores in said plurality of storage elements an input signal received from said bidirectional pin and an output signal to be transmitted on said bidirectional pin.

17. The apparatus of claim 16, wherein said first integrated circuit further comprises:

a processor data bus; and

a processor address bus;

wherein said plurality of storage elements are coupled to said processor data bus and said processor address bus so that a processor coupled to said processor data bus and to said processor address bus can load data into said plurality of storage elements.

18. The apparatus of claim 16, wherein the duration of said predetermined time period is at least two cycles in a clock signal.

19. The apparatus of claim 16 wherein the first integrated circuit further comprises:

a fist plurality of pins couplable to a first bus;

a second plurality of pins couplable to a second bus; and

a data transfer circuit connected to said first and second pluralities of pins;

wherein said data transfer circuit transfers information between said first plurality of pins and said second pluralities of pins; and

wherein said first bus is an input and output bus connected to a peripheral device and said second bus is a system bus connected to a host processor.

20. The apparatus of claim 19 wherein:

said system bus is coupled to said first serial port; and

said first serial port further comprises a command generator circuit having a serial port input-output bus coupled to said system bus, and a parallel output bus wherein in response to a signal on said serial input-output bus, said command generator circuit drives a command signal on said parallel bus.