Pipelined asynchronous processing

• US 6,381,692 B1
• Filed: 07/16/1998
• Issued: 04/30/2002
• Est. Priority Date: 07/16/1997
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Nystrom, Mika, Manohar, Rajit, Lines, Andrew, Cummings, Uri, Martin, Alain J.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): WHITMORE, STACY
• Application Number:
  US09/118,140
• Time in Patent Office: 1,384 Days
• Field of Search: 712/18, 712/23, 712/25, 712/41, 712/210, 712/216, 712/219, 712/244
• US Class Current: 712/244
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages

Abstract

An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Claims

1. A system, comprising:

a plurality of execution units, each independently capable of executing information contained in an instruction, and each operating to complete operation of an instruction and signal its readiness to complete another instruction in a time it takes to finish executing the instruction, without reference to a common system clock;

an instruction obtaining part including a program counter coordinating obtaining instructions from an instruction memory;

a first cache memory, including designations associated with said plurality of execution units, stored in an order which represents an order of execution by instructions in said plurality of execution units;

a second cache memory, including information on instructions which are to be executed by said plurality of execution units; and

a write back unit, responsive to said first and second cache memories, and operating to detect an exception, and to cancel writing from said execution units in response to said exception, and reconstructing unit order based on information in said first cache memory and determining which instruction causes the exception based on information in said second cache memory, otherwise discarding the information in said second cache memory.

2. A system as in claim 1, wherein each of said execution units is coupled to said write back unit, and communicates information about said exception to said write back unit.

3. A system as in claim 2, wherein said write back unit is also responsive to a pseudo instruction which restores values in the registers.

4. A system as in claim 1, wherein said execution units include at least a memory unit and at least one arithmetic logic unit.

5. A system as in claim 4, further comprising a plurality of register units including register parts, selectively connected to said execution units.

6. A system as in claim 5, wherein said write back unit cancels writing from said execution units to at least one of said register parts in response to said detection of said exception.

7. A system as in claim 1, wherein said instruction obtaining part includes a fetching unit, responsive to said program counter unit, to receive information from said program counter unit.

8. A system as in claim 7, further comprising an instruction memory unit, which includes instruction information, said instruction memory unit responsive to said fetch unit to provide instruction information responsive thereto.

9. A system as in claim 8, further comprising a decoder, coupled to said fetch unit, to receive information therefrom.

10. A method, comprising:

obtaining a plurality of instructions in an asynchronous processor, to be executed substantially simultaneously, in a pipelined fashion;

in each of a plurality of execution units, receiving one of said instructions, and executing and completing said instruction in the time it takes to execute and complete said instruction independent of a comment system clock, and requesting and next instruction when completed, independent of said comment system clock;

storing designations associated with said plurality of execution units in a first cachememory, said designations being stored in an order that represents an order of execution;

storing instruction information associated with said plurality of execution units in a second cachememory, said instruction information including information about the instructions being propped by said he plurality of execution units; and

detecting and exception in any of said execution units, and using said designations information and said instruction information to restore the execution to based on said exception; and

otherwise, when no in exception is detected, discarding at least said instruction information from said second cachememory.

11. A method as in claim 10, wherein said instructions include instructions that are executed in an arithmetic logic unit.

12. A method as in claim 10, further comprising, responsive to detecting said exception, preventing of execution unit with caused said exception from completing a memory operation associated with the instruction that caused the exception.