Pipelined asynchronous processing
First Claim
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1. A system, comprising:
- a plurality of execution units, each independently capable of executing information contained in an instruction, and each operating to complete operation of an instruction and signal its readiness to complete another instruction in a time it takes to finish executing the instruction, without reference to a common system clock;
an instruction obtaining part including a program counter coordinating obtaining instructions from an instruction memory;
a first cache memory, including designations associated with said plurality of execution units, stored in an order which represents an order of execution by instructions in said plurality of execution units;
a second cache memory, including information on instructions which are to be executed by said plurality of execution units; and
a write back unit, responsive to said first and second cache memories, and operating to detect an exception, and to cancel writing from said execution units in response to said exception, and reconstructing unit order based on information in said first cache memory and determining which instruction causes the exception based on information in said second cache memory, otherwise discarding the information in said second cache memory.
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Abstract
An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.
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Citations
12 Claims
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1. A system, comprising:
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a plurality of execution units, each independently capable of executing information contained in an instruction, and each operating to complete operation of an instruction and signal its readiness to complete another instruction in a time it takes to finish executing the instruction, without reference to a common system clock;
an instruction obtaining part including a program counter coordinating obtaining instructions from an instruction memory;
a first cache memory, including designations associated with said plurality of execution units, stored in an order which represents an order of execution by instructions in said plurality of execution units;
a second cache memory, including information on instructions which are to be executed by said plurality of execution units; and
a write back unit, responsive to said first and second cache memories, and operating to detect an exception, and to cancel writing from said execution units in response to said exception, and reconstructing unit order based on information in said first cache memory and determining which instruction causes the exception based on information in said second cache memory, otherwise discarding the information in said second cache memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method, comprising:
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obtaining a plurality of instructions in an asynchronous processor, to be executed substantially simultaneously, in a pipelined fashion;
in each of a plurality of execution units, receiving one of said instructions, and executing and completing said instruction in the time it takes to execute and complete said instruction independent of a comment system clock, and requesting and next instruction when completed, independent of said comment system clock;
storing designations associated with said plurality of execution units in a first cachememory, said designations being stored in an order that represents an order of execution;
storing instruction information associated with said plurality of execution units in a second cachememory, said instruction information including information about the instructions being propped by said he plurality of execution units; and
detecting and exception in any of said execution units, and using said designations information and said instruction information to restore the execution to based on said exception; and
otherwise, when no in exception is detected, discarding at least said instruction information from said second cachememory. - View Dependent Claims (11, 12)
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Specification