Methods of forming thin-film transistor display devices
First Claim
1. A method of forming a thin-film transistor display device, comprising the steps of:
- forming an insulated gate electrode on a face of a substrate;
forming a semiconductor layer on the insulated gate electrode, opposite the face;
forming spaced apart source and drain electrodes which each comprise a composite of at least two layers containing respective metals of different element type therein, on the semiconductor layer; and
forming a pixel electrode electrically coupled to said drain electrode.
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Abstract
Thin-film transistor display devices include composite electrodes which provide low resistance contacts and paths for electrical signals and are less susceptible to parasitic metal migration which can limit display quality and lifetime. In particular, a thin-film transistor (TFT) display device is provided having an insulated gate electrode on a face of a substrate (e.g., transparent substrate) and a semiconductor layer on the insulated gate electrode, opposite the face of the substrate. Spaced apart source and drain electrodes are also provided on the semiconductor layer. These source and drain electrodes each preferably comprise a composite of at least two layers containing respective metals therein of different element type. Preferably, one of the layers comprises a metal which is capable of forming a low resistance contact with electrodes such as a pixel electrode (e.g., transparent indium-tin-oxide electrode) and the other of the layers comprises a relatively low resistance metal so that the overall effective resistance of each composite electrode is maintained at a low level.
14 Citations
12 Claims
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1. A method of forming a thin-film transistor display device, comprising the steps of:
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forming an insulated gate electrode on a face of a substrate;
forming a semiconductor layer on the insulated gate electrode, opposite the face;
forming spaced apart source and drain electrodes which each comprise a composite of at least two layers containing respective metals of different element type therein, on the semiconductor layer; and
forming a pixel electrode electrically coupled to said drain electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
forming a gate electrode comprising a composite of at least two layers containing respective metals therein of different element type, on the face of the substrate; and
forming a gate electrode insulating layer on the gate electrode.
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3. The method of claim 2, wherein said step of forming a semiconductor layer comprises the steps of:
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forming a first amorphous silicon layer on the gate electrode insulating layer; and
forming a second amorphous silicon layer containing dopants of predetermined conductivity type therein, on the first amorphous silicon layer, opposite the gate electrode insulating layer.
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4. The method of claim 3, wherein said step of forming spaced apart source and drain electrodes comprises the steps of:
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forming a first metal layer containing a refractory metal selected from the group consisting of chromium, molybdenum, titanium and tantalum, on the second amorphous silicon layer;
forming a second metal layer containing aluminum, on the first metal layer; and
patterning the first and second metal layers into spaced apart source and drain electrodes.
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5. The method of claim 4, wherein said step of forming a pixel electrode comprises the steps of forming a pixel electrode in ohmic contact with the patterned first metal layer.
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6. The method of claim 5, wherein said step of forming a first amorphous silicon layer comprises depositing a first amorphous silicon layer having a thickness of about 2000 Å
- on the gate electrode insulating layer; and
wherein said step of forming a second amorphous silicon layer comprises depositing a second amorphous silicon layer containing dopants therein of predetermined conductivity type and having a thickness of about 500 Å
, on the first amorphous silicon layer.
- on the gate electrode insulating layer; and
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7. The method of claim 5, wherein said step of forming spaced apart source and drain electrodes comprises the steps of:
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forming a first metal layer having a thickness of about 1000 Å
, on the second amorphous silicon layer; and
forming a second metal layer having a thickness of about 2000 Å
on the first metal layer.
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8. The method of claim 7, wherein said step of forming a pixel electrode is preceded by the step of wet etching the patterned second metal layer to expose the patterned first metal layer.
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9. The method of claim 1, wherein said step of forming spaced apart source and drain electrodes comprises the steps of:
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forming a first metal layer containing a refractory metal selected from the group consisting of chromium, molybdenum, titanium and tantalum, on the semiconductor layer;
forming a second metal layer containing aluminum, on the first metal layer; and
patterning the first and second metal layers into spaced apart source and drain electrodes.
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10. The method of claim 9, wherein said step of forming a pixel electrode comprises the steps of forming a pixel electrode in ohmic contact with the patterned first metal layer.
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11. The method of claim 10, wherein said step of forming spaced apart source and drain electrodes comprises the steps of:
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forming a first metal layer having a thickness of about 1000 Å
, on the semiconductor layer; and
forming a second metal layer having a thickness of about 2000 Å
on the first metal layer.
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12. The method of claim 11, wherein said step of forming a pixel electrode is preceded by the step of wet etching the patterned second metal layer to expose the patterned first metal layer.
Specification