Interdigitated capacitor structure for use in an integrated circuit

• US 6,383,858 B1
• Filed: 02/16/2000
• Issued: 05/07/2002
• Est. Priority Date: 02/16/2000
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Gupta, Rohini, Tauke, John D.
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/505,762
• Time in Patent Office: 811 Days
• Field of Search: 438/238, 438/250-256, 438/331, 438/393-399
• US Class Current: 438/238
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a capacitor structure comprising an array having two dimensions and having first and second electrode elements alternating in both dimensions of the array, the first electrode elements interconnected and the second electrode elements interconnected, to cause the array to function as a capacitor. The capacitor structure further comprises a dielectric material, which in one embodiment may be silicon dioxide (SiO₂), separating the first and second electrode elements in both of the dimensions. In one embodiment of the invention, the first electrode elements are interconnected by a first interconnect, and the second electrode elements are interconnected by a second interconnect, allowing the first and second electrode elements to function as an interdigitated capacitor.

Claims

1. A method of fabricating a capacitor structure, comprising:

forming an array having two dimensions wherein a width of the array is about 25 μ

m, and having first and second electrode elements alternating in both dimensions of the array, the first electrode elements interconnected and the second electrode elements interconnected, to cause the array to function as a capacitor where a ratio of a capacitance of the array to a capacitance of a stacked capacitor having a same area as the array is about 2; and

forming dielectric material between the first and second electrode elements in both of the dimensions.

2. The method as recited in claim 1 wherein forming the array includes interconnecting the first electrode elements by a first interconnect and interconnecting the second electrode elements by a second interconnect.

3. The method as recited in claim 1 wherein forming a dielectric material between the first and second electrode elements includes forming silicon dioxide.

4. The method as recited in claim 1 wherein fabricating the capacitor structure includes fabricating the capacitor structure to a width of about 50 μ

m wherein the capacitor structure has a capacitance value of about 20 fF/μ

m.

5. The method as recited in claim 1 wherein forming the array includes forming first and second electrode elements with copper.

6. The method as recited in claim 5 further comprising forming a barrier layer located between the first and second electrode elements, and the dielectric material.

7. The method as recited in claim 6 wherein forming a barrier layer includes forming a barrier layer with tantalum nitride.

8. The method as recited in claim 1 wherein forming an array includes forming first and second electrode elements comprised of a conductive material selected from the group consisting of:

doped polysilicon,

titanium nitride, and

aluminum.

9. The method as recited in claim 1 wherein the array has a gained capacitance of about 0.4 fF/μ

m for each of the first or second electrode elements.