Method of forming multiple oxide thicknesses for merged memory and logic applications

• US 6,383,871 B1
• Filed: 08/31/1999
• Issued: 05/07/2002
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PERT, EVAN T
• Application Number:
  US09/386,185
• Time in Patent Office: 980 Days
• Field of Search: 438/275, 438/769, 438/770, 438/198, 438/270
• US Class Current: 438/275
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Improved methods and structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, improved methods and structures are provided for multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. Moreover, these improved methods and structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method for forming a semiconductor device include forming a top layer of SiO₂ on a top surface of a silicon wafer. A trench layer of SiO₂ is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO₂ are such that a thickness of the top layer is different from a thickness of the trench layer.

Claims

1. A method for forming a semiconductor device, comprising:

forming two different gate oxides for different transistors on a substrate by;

forming a top layer of SiO₂ on a top surface of a silicon wafer; and

forming a trench layer of SiO₂ on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, wherein a thickness of the top layer is different from a thickness of the trench layer, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800°

C.

2. The method of claim 1, wherein forming the top layer of SiO₂ includes forming a gate oxide of a logic device.

3. The method of claim 1, wherein forming the trench layer of SiO₂ includes forming a gate oxide of a DRAM cell.

4. The method of claim 1, wherein forming the top layer of SiO₂ and forming the trench layer of SiO₂ includes forming the top layer of SiO₂ and forming the trench layer of SiO₂ simultaneously during a linear growth period.

5. The method of claim 1, wherein forming the top layer of SiO₂ on the top surface of the silicon wafer includes thermally growing the top layer of SiO₂ on the top surface of the silicon wafer.

6. The method of claim 1, wherein forming the trench layer of SiO₂ on the trench wall of the silicon wafer includes thermally growing the trench layer of SiO₂ on the trench wall of the silicon wafer.

7. A method for forming a semiconductor device, comprising:

forming two different gate oxides for different transistors on a substrate by;

forming a top surface of a silicon wafer with a top crystalline plane orientation;

forming a trench in the silicon wafer, wherein a trench wall has a different crystalline plane orientation than the top crystalline plane orientation; and

simultaneously thermally growing a top oxide layer on the top surface and thermally growing a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer, the trench oxide layer having a thickness that is greater than the thickness of the top oxide layer.

8. The method of claim 7, wherein thermally growing the top oxide layer on the top surface and thermally growing the trench oxide layer on the trench wall includes thermally growing the trench oxide layer that has a thickness that is approximately 30% thicker than a thickness of the top oxide layer.

9. The method of claim 7, wherein thermally growing the top oxide layer includes thermally growing the top oxide layer such that the thickness of the top oxide layer is approximately 70 Angstroms.

10. The method of claim 7, wherein thermally growing the trench oxide layer includes thermally growing the trench oxide layer such that the thickness of the trench oxide layer is approximately 100 Angstroms.

11. A method for forming a semiconductor device, comprising:

forming two different gate oxides for different transistors on a substrate by;

forming a trench in a silicon wafer, the silicon wafer having a top surface, the trench having a trench wall, such that the trench wall has a (110) crystal plane orientation, wherein the top surface has a (100) crystal plane orientation; and

simultaneously thermally oxidizing the top surface to a top thickness and oxidizing the trench wall at a temperature of approximately 800°

C. to a trench thickness that is different from the top thickness.

12. The method of claim 11, wherein oxidizing the top surface includes dry oxidizing the top surface at a temperature of approximately 800°

C.

13. The method of claim 11, wherein oxidizing the trench wall includes dry oxidizing the trench wall at a temperature of approximately 800°

C.

14. A method for forming a semiconductor device, comprising:

forming a top layer of SiO₂ on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, such that the top layer has a top thickness; and

forming a trench layer of SiO₂ on a trench wall of the silicon wafer, wherein the trench wall has a (311) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer, wherein forming the top layer of SiO₂ and forming the trench layer of SiO₂ includes forming the top layer of SiO₂ and forming the trench layer of SiO₂ simultaneously during a linear growth period, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800°

C.

15. A method of forming a semiconductor device, comprising:

forming a top surface of a silicon wafer with a (110) crystalline plane orientation;

forming a trench in the silicon wafer, wherein a trench wall has a (511) crystalline plane orientation; and

simultaneously thermally growing a top oxide layer on the top surface and thermally growing a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800°

C.

16. A method for forming a semiconductor device, comprising:

forming two different gate oxides for different transistors on a substrate by;

forming a top layer of SiO₂ on a top surface of a silicon wafer;

forming a trench layer of SiO₂ on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, wherein a thickness of the top layer is less than a thickness of the trench layer, wherein forming the top layer includes forming a gate oxide of a top device operating with a voltage of less than about 2.5 volts, and forming the trench layer includes forming a gate oxide of a trench device operating with a voltage of less than about 3.5 volts.

17. The method of claim 16 wherein the trench layer is formed having a thickness approximately 30% thicker than the top layer.

18. The method of claim 16 wherein the thickness of the trench layer formed is approximately 100 Angstroms.

19. The method of claim 16 wherein the thickness of the top layer formed is approximately 70 Angstroms.

20. The method of claim 16 wherein forming the trench layer includes forming a trench gate oxide formed to function in a trench device.

21. The method of claim 20 wherein the trench layer is adapted for use with a DRAM cell.

22. The method of claim 20 wherein the trench device is an EEPROM device.

23. The method of claim 22 wherein the trench device includes a flash memory device.

24. The method of claim 20 wherein the trench device is included as part of a programmable logic array.

25. The method of claim 16 wherein the semiconductor device further comprises a top device including a top gate separated from the top surface by a top gate oxide.

26. The method of claim 25 wherein the top device is a logic device.

27. The method of claim 16 wherein the trench layer is formed on the trench wall through dry oxidization at a temperature of approximately 800°

C.

28. The method of claim 16 wherein the trench layer is formed on the trench wall through wet oxidization at a temperature of approximately 800°

C.

29. A method for forming a semiconductor device, comprising:

forming two different gate oxides for different transistors on a substrate by;

forming a top layer of SiO₂ on a top surface of a silicon wafer;

forming a trench layer of SiO₂ on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, the trench wall has a crystal plane orientation selected from the group consisting of (100), (110), (311), and (511) crystal plane orientations, and the top surface has a crystal plane orientation selected from the group consisting of (100), (110), and (111) crystal plane orientations, and wherein a thickness of the top layer is greater than a thickness of the trench layer.