MOS device having non-uniform dopant concentration and method for fabricating the same

• US 6,383,876 B1
• Filed: 07/27/2000
• Issued: 05/07/2002
• Est. Priority Date: 05/06/1997
• Status: Expired due to Fees

• Current Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Son, Jeong Hwan, Huh, Ki Jae
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US09/627,298
• Time in Patent Office: 649 Days
• Field of Search: 438/289, 438/290, 438/291, 438/303, 438/305, 438/585, 438/595
• US Class Current: 438/289
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing the polysilicon using a semirecessed LOCOS process. The present invention is directed most generally to a semiconductor device which includes: a semiconductor substrate of a first conductivity type; a gate insulator on the substrate, the gate insulator sharing an interface with the substrate; a gate electrode on the gate insulator, the gate electrode having a first side, a second side, and a middle region between the first and second sides; a source doped region of a second conductivity type within the substrate to the first side of the gate electrode and a drain doped region of the second conductivity type within the substrate to the second side of the gate electrode, the source and drain doped regions self-aligned to the gate electrode; and a channel doped region of the first conductivity type within the substrate below the gate electrode, the channel doped region having a peak dopant concentration profile such that the peak dopant concentration under the middle region of the gate electrode occurs further below the gate insulator-substrate interface than does either the peak dopant concentration under the first side of the gate electrode or the peak dopant concentration under the second side of the gate electrode.

Claims

1. A method of fabricating a semiconductor device on a substrate of a first conductivity type, the method comprising the steps of:

forming a polysilicon layer over the substrate, the polysilicon layer having a depression in a first region that will subsequently be included in a gate electrode;

forming a doped channel region of the first conductivity type within the substrate, the doped channel region having a peak dopant concentration profile corresponding to the depression in the polysilicon layer;

etching the polysilicon layer to form a polysilicon gate electrode that includes the first region of the polysilicon layer, the gate electrode having a first side and a second side; and

forming first doped source/drain regions of a second conductivity type within the substrate to either side of the gate electrode, the first doped source/drain regions self-aligned to the gate electrode,

wherein the step of forming a polysilicon layer over the substrate includes the sub-steps of;

forming a first insulating layer on the substrate, the first insulating layer having an interface with the substrate;

depositing a polysilicon layer on the first insulating layer;

depositing a second insulating layer on the polysilicon layer;

etching the second insulating layer to expose a first region of the polysilicon layer that will subsequently be included in a gate electrode;

forming a third insulating layer on the first exposed region of the polysilicon layer, thereby forming a concave-up depression in the polysilicon layer; and

removing the third insulating layer from the polysilicon layer.

2. The method according to claim 1, wherein the step of

etching the polysilicon layer to form a polysilicon gate electrode that includes the first region of the polysilicon layer

includes the sub-steps of

forming a fourth insulating layer in the concave-up depression of the polysilicon layer;

etching the second insulating layer and the polysilicon layer, thereby exposing a region of the first insulating layer and forming a gate electrode having the concave-up depression in which the fourth insulating layer has been formed;

depositing a fifth insulating layer on the exposed region of the first insulating layer and on the fourth insulating layer; and

etching the fifth insulating layer to form gate sidewall spacers on the first insulating layer, contiguous to either side of the gate electrode.

3. The method according to claim 2, further comprising the step of:

implanting dopants of the second conductivity type to form within the substrate to either side of the gate electrode second source and drain doped regions of the second conductivity type more heavily doped than the first source and drain doped regions, the more heavily doped source and drain regions self-aligned to the sidewall spacers contiguous to the gate electrode.