Top layers of metal for high performance IC's
First Claim
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1. A method for forming a top metallization system for high performance integrated circuits, comprising:
- forming an integrated circuit containing a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and containing a plurality of first metal lines in one or more layers;
depositing a passivation layer over said interconnecting metallization structure;
depositing an insulating, separating layer of polymer over said passivation layer that is substantially thicker than said passivation layer;
forming openings through said polymer insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metallization structure;
depositing metal contacts in said openings; and
forming said top metallization system connected to said overlaying interconnecting metallization structure, wherein said top metallization system contains a plurality of top metal lines, in one or more layers, each of said top metal lines having a width substantially greater than said first metal lines.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
338 Citations
48 Claims
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1. A method for forming a top metallization system for high performance integrated circuits, comprising:
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forming an integrated circuit containing a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and containing a plurality of first metal lines in one or more layers;
depositing a passivation layer over said interconnecting metallization structure;
depositing an insulating, separating layer of polymer over said passivation layer that is substantially thicker than said passivation layer;
forming openings through said polymer insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metallization structure;
depositing metal contacts in said openings; and
forming said top metallization system connected to said overlaying interconnecting metallization structure, wherein said top metallization system contains a plurality of top metal lines, in one or more layers, each of said top metal lines having a width substantially greater than said first metal lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 45)
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21. A method for forming a top metallization system for high performance integrated circuits, comprising:
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forming an integrated circuit containing a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting-metallization structure connected to said devices and containing a plurality of first metal lines;
depositing a polymer insulating, separating layer over said semiconductor substrate;
forming openings through said polymer insulating, separating layer to expose upper metal portions of said interconnecting metallization structure;
depositing metal contacts in said openings; and
forming said top metallization-system connected to said interconnecting metallization structure, wherein said top metallization system contains a plurality of top metal lines, in one or more layers, having a width substantially greater than said first metal lines. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A method for forming a top metallization system for high performance integrated circuits, comprising:
- forming an integrated circuit containing a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and containing a plurality of fine-wire metal lines;
depositing a passivation layer over said interconnecting fine-wire metallization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer;
forming openings through said polymer insulating, separating layer to expose upper metal portions of said overlaying interconnecting metallization structure;
depositing metal contacts in said openings thereby raising a plurality of contact points in said overlaying interconnecting metallization structure to a top surface of said polymer insulating, separating layer thereby creating elevated interconnecting metallization contact points;
forming said top metallization system connected to said overlaying interconnecting metallization structure, wherein said top metallization system contains a plurality of top wide-metal lines, in one or more layers, having a width substantially greater than said fine-wire metal lines, wherein said top metallization system directly interconnects said elevated interconnecting metallization contact points thereby functionally extending or connecting said fine-wire metal interconnects with said wide-wire metal interconnects thereby furthermore establishing electrical interconnects between multiple points within said fine-wire interconnects. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
- forming an integrated circuit containing a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and containing a plurality of fine-wire metal lines;
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46. A method for forming a top metallization system for high performance integrated circuits comprising:
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forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, wherein intermetal dielectric layers are formed between said plurality of first metal lines;
depositing a passivation layer over said interconnecting metallization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than each of said intermetal dielectric layers;
forming openings through said polymer insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metallization structure;
depositing metal contacts in said openings; and
forming said top metallization system connected to said overlaying interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, each of said top metal lines having a width substantially greater than said first metal lines. - View Dependent Claims (47)
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48. A method for forming a top metallization system for high performance integrated circuits comprising:
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forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, wherein intermetal dielectric layers are formed between said plurality of first metal lines;
depositing a passivation layer over said interconnecting metallization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than each of said intermetal dielectric layers;
forming openings through said polymer insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metallization structure;
depositing metal contacts in said openings; and
forming said top metallization system connected to said overlaying interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, each of said top metal lines having a thickness substantially greater than said first metal lines.
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Specification