Article comprising vertically nano-interconnected circuit devices and method for making the same

• US 6,383,923 B1
• Filed: 08/22/2000
• Issued: 05/07/2002
• Est. Priority Date: 10/05/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Jin, Sungho, Zhu, Wei, Brown, Walter L.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Thanh V
• Application Number:
  US09/643,784
• Time in Patent Office: 623 Days
• Field of Search: 438/666, 438/962, 257/734
• US Class Current: 438/666
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/11003 for holding or transferring the bump preform
• CPC Class Codes: H01L 2224/111 Manufacture and pre-treatment of the bump connector preform
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/13193 with a principal constituent of the material being a solid not provided for in groups H01L2224/131 - H01L2224/13191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H10K 10/701 : Organic molecular electronic devices
• CPC Class Codes: Y10S 438/962 : Quantum dots and lines
• CPC Class Codes: Y10S 977/762 : Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/848 : Tube end modifications, e.g. capping, joining, splicing

Abstract

A circuit device is disclosed comprising at least two circuit layers or circuit devices vertically interconnected with a plurality of parallel and substantially equi-length nanowires disposed therebetween. The nanowires may comprise composites, e.g., having a heterojunction present along the length thereof, to provide for a variety of device applications. Also disclosed is a method for making the circuit device comprising growing a plurality of nanowires on a dissolvable or removable substrate, equalizing the length of the nanowires (e.g., so that each one of the plurality of nanowires is substantially equal in length), transferring and bonding exposed ends of the plurality of nanowires to a first circuit layer; and removing the dissolvable substrate. The nanowires attached to the first circuit layer then can be further bonded to a second circuit layer to provide the vertically interconnected circuit device.

Claims

1. A method of making a circuit device comprising:

providing a substrate;

growing a plurality of spaced-apart carbon nanotubes attached on the substrate so that each one of the plurality of nanotubes has a first exposed end and a second end attached to the substrate;

while the nanotubes are attached to the substrate, equalizing the length of the nanotubes so that each one of the plurality of nanotubes is substantially equal in length with a length variation of less than 20%;

bonding the resulting exposed ends of the plurality of nanotubes to a first circuit layer; and

removing the substrate to provide a circuit device having the plurality of nanotubes bonded to the first circuit layer with the second ends of the plurality of nanotubes exposed.

2. The method of claim 1, wherein the step of removing the substrate comprises mechanically detaching the second ends of the plurality of nanotubes from the substrate.

3. The method of claim 1 wherein the substrate comprises a dissolvable substrate and the step of removing the substrate comprises chemically dissolving the substrate.

4. The method of claim 1 further comprising the steps of providing a second circuit layer, coating the second exposed ends of the plurality of nanotubes with a second soldering material, and bonding the second exposed ends to the second circuit layer to provide a vertically-interconnected circuit device.

7. The method of claim 1 further comprising the step of coating at least one of the exposed ends of the plurality of nanowires with a soldering material.

8. The method of claim 7 in which the soldering material is applied to at least one of the exposed ends of the plurality of nanowires by a deposition process during which the dissolvable substrate is rotated to promote a uniform application of the soldering material on the plurality of nanowires.

9. The method of claim 7 in which the first and second circuit layers each has a plurality of contact pads thereon, a layer of soldering material is applied to each of the contact pads on the resulting exposed ends and second circuit layer, and the first and second ends of the plurality of nanowires are bonded onto the contact pads.

10. The method of claim 9, in which the first soldering material used to bond the first exposed ends to the first circuit layer has a first soldering temperature and the second soldering material used to bond the second exposed ends to the second circuit layer has a second soldering temperature, in which the second soldering temperature is lower than the first soldering temperature.

11. The method of claim 1, in which the step of equalizing the length of the nanowires comprises:

partially embedding the plurality of nanowires attached to the dissolvable substrate in a layer of sacrificial material of substantially uniform thickness whereby an extra length of nanowires protrudes from the sacrificial material;

removing the extra length of nanowires; and

removing the sacrificial material.

12. The method of claim 11, further comprising a conductive underlayer interposed between the dissolvable substrate and the catalytic nucleation layer for use in enhancing adherence of the layer of sacrificial material to the dissolvable substrate.

13. The method of claim 11, in which the sacrificial material is deposited by electroplating.

14. The method of claim 11, in which the thickness of the layer of sacrificial material is in the range of about 1 to 100 micrometers.

5. A method of making a circuit device comprising:

providing a dissolvable substrate growing a plurality of nanowires on the substrate so that each one of the plurality of nanowires has a first exposed end and a second end attached to the substrate, said growing the plurality of nanowires comprises depositing a catalytic nucleation layer on the dissolvable substrate and decomposing a gas adjacent the catalytic nucleation layer;

equalizing the length of the nanowires so that each one of the plurality of nanowires is substantially equal in length;

bonding the resulting exposed ends of the plurality of nanowires to a first circuit layer; and

removing the substrate to provide a circuit device having a plurality of nanowires bonded to the first circuit layer with the second ends of the plurality of nanowires exposed.

6. The method of claim 5 in which the gas comprises a hydrocarbon-containing gas such that carbon nanotubes are grown on the dissolvable substrate.