Field-effect transistor having a high packing density and method for fabricating it

• US 6,384,456 B1
• Filed: 03/30/2000
• Issued: 05/07/2002
• Est. Priority Date: 09/30/1997
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tihanyi, Jenoe
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Thanh V
• Application Number:
  US09/538,793
• Time in Patent Office: 768 Days
• Field of Search: 257/401, 257/288, 438/589, 438/FOR.197
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A field-effect transistor has a semiconductor body with a main area, in which at least one source zone and one drain zone are introduced and which is provided with a gate electrode isolated from a channel region disposed between a source zone and a drain zone by an insulator layer. In the field-effect transistor, the source zone, the drain zone and the channel region are disposed in walls of a respective trench or recess formed in the semiconductor body.

Claims

1. A field-effect transistor, comprising:

a semiconductor body having a main area with isolated trenches formed therein, including a first trench, a second trench and a third trench, said semiconductor body having walls defining each of said trenches;

at least one source zone disposed in said walls defining said first trench;

at least one drain zone disposed in said walls defining said third trench;

a channel region disposed in said walls defining said second trench and disposed between said source zone and said drain zone;

an insulator layer disposed in said semiconductor body;

a gate electrode isolated from said channel region by said insulator layer;

a source electrode disposed in said first trench; and

a drain electrode disposed in said third trench.

2. The field-effect transistor according to claim 1, wherein said trenches each have an substantially round cross section.

3. The field-effect transistor according to claim 1, wherein said second trench for said channel region is disposed between said first trench and said third trench such that said source zone and said drain zone each make contact with said insulator layer.

4. The field-effect transistor according to claim 1, wherein said gate electrode, said source electrode and said drain electrode are composed of heavily doped polycrystalline silicon.

5. The field-effect transistor according to claim 1, wherein said semiconductor body is p-doped.

6. The field-effect transistor according to claim 1, wherein said drain zone has a doping concentration that rises toward said drain electrode.

7. The field-effect transistor according to claim 1, including an insulating material embedding said semiconductor body.

8. The field-effect transistor according to claim 1, including an insulator and said semiconductor body is disposed on said insulator.

9. The field-effect transistor according to claim 1, including at least one of titanium nitride and a silicide disposed in said walls of said trenches.

10. The field-effect transistor according to claim 1, wherein said semiconductor body has a further trench formed therein for a terminal.

11. The field-effect transistor according to claim 1, wherein said source zone and said drain zone are doped with at least one of arsenic and phosphorus.

12. The field-effect transistor according to claim 1, including a doped zone disposed underneath said gate electrode.

13. The field-effect transistor according to claim 12, wherein said semiconductor body has a given conductivity type and said doped zone has a conductivity type that is the same as said given conductivity type of said semiconductor body.

14. The field-effect transistor according to claim 1, wherein said drain electrode, said gate electrode and said source electrode form layers of interconnects.

15. The field-effect transistor according to claim 14, wherein said interconnects are disposed in different planes.

16. The field-effect transistor according to claim 1, wherein said trenches each have a diameter of from 0.1 to 1 μ

m and center lines at a distance of approximately 0.1 to 1 μ

m from one another.

17. A dynamic random access memory, comprising:

a field-effect transistor, including;

a semiconductor body having a main area with isolated trenches formed therein, including a first trench, a second trench and a third trench, said semiconductor body having walls defining each of said trenches;

at least one source zone disposed in said walls defining said first trench;

at least one drain zone disposed in said walls defining said third trench;

a channel region disposed in said walls defining said second trench and disposed between said source zone and said drain zone;

an insulator layer disposed in said semiconductor body;

a gate electrode isolated from said channel region by said insulator layer;

a source electrode disposed in said first trench; and

a drain electrode disposed in said third trench.

18. A CMOS-integrated circuit, comprising:

a field-effect transistor, including;

a semiconductor body having a main area with isolated trenches formed therein, including a first trench, a second trench and a third trench, said semiconductor body having walls defining each of said trenches;

at least one source zone disposed in said walls defining said first trench;

at least one drain zone disposed in said walls defining said third trench;

a channel region disposed in said walls defining said second trench and disposed between said source zone and said drain zone;

an insulator layer disposed in said semiconductor body;

a gate electrode isolated from said channel region by said insulator layer;

a source electrode disposed in said first trench; and

a drain electrode disposed in said third trench.