Logic block used as dynamically configurable logic function
First Claim
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1. In an FPGA, comprising:
- I. a general interconnect structure; and
II. an array of logic blocks, each logic block comprising;
a. a lookup table configurable as a shift register, the lookup table having a shift register input terminal, a plurality of data input terminals and an output terminal;
b. a carry multiplexer controlled by the output terminal of the lookup table, having i. an output terminal, ii. a first input terminal that may be coupled to the output terminal of another carry multiplexer, and iii. a second input terminal;
c. an AND gate having an output terminal connectable to the second input terminal of the carry multiplexer and two input terminals connected to two of the plurality of data input terminals of the lookup table;
a programmable comparator for comparing at least one value on at least one of the plurality of input terminals of the lookup table to at least one other value, the programmable comparator having two modes, a loading mode and an operating mode, whereinin the loading mode a clock signal causes a bitstream to be shifted from the shift register input terminal into the lookup table; and
in the operating mode the bitstream in the lookup table performs a comparison function implemented such that a successful comparison causes the carry multiplexer to connect to its output terminal an input terminal whose value represents the successful comparison, and a failed comparison causes the carry multiplexer to connect to its output terminal an input terminal whose value represents a failed result.
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Abstract
A method of configuring an FPGA lookup table to implement both exact and relative matching comparators is disclosed. Examples of exact matching of two variables, exact matching of a variable to a constant, relative matching (greater than) of a variable to a constant, and combined exact and relative matching are discussed. Use of the comparator to trigger a logic analyzer to collect data is discussed.
54 Citations
21 Claims
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1. In an FPGA, comprising:
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I. a general interconnect structure; and
II. an array of logic blocks, each logic block comprising;
a. a lookup table configurable as a shift register, the lookup table having a shift register input terminal, a plurality of data input terminals and an output terminal;
b. a carry multiplexer controlled by the output terminal of the lookup table, having i. an output terminal, ii. a first input terminal that may be coupled to the output terminal of another carry multiplexer, and iii. a second input terminal;
c. an AND gate having an output terminal connectable to the second input terminal of the carry multiplexer and two input terminals connected to two of the plurality of data input terminals of the lookup table;
a programmable comparator for comparing at least one value on at least one of the plurality of input terminals of the lookup table to at least one other value, the programmable comparator having two modes, a loading mode and an operating mode, wherein in the loading mode a clock signal causes a bitstream to be shifted from the shift register input terminal into the lookup table; and
in the operating mode the bitstream in the lookup table performs a comparison function implemented such that a successful comparison causes the carry multiplexer to connect to its output terminal an input terminal whose value represents the successful comparison, and a failed comparison causes the carry multiplexer to connect to its output terminal an input terminal whose value represents a failed result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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- 17. An FPGA configuration wherein a portion of the configuration is a logic analyzer for providing information to a user about operation of another portion of the configuration, and wherein part of the configuration of the logic analyzer is determined when the FPGA is configured and another part of the configuration of the logic analyzer is determined by another portion of the logic analyzer.
Specification