Techniques for programming programmable logic array devices

• US 6,384,630 B2
• Filed: 01/12/2001
• Issued: 05/07/2002
• Est. Priority Date: 06/05/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Raman, Rina, Terrill, Richard Shaw, Sung, Chiakang, Veenstra, Kerry, Cliff, Richard G., Reddy, Srinivas T., Papaliolios, Andreas, Bielby, Robert Richard Noel
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/760,231
• Publication Number:
  US 20010003844A1
• Time in Patent Office: 480 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Claims

1. An apparatus to program a plurality of programmable logic devices (PLDS) located on respective integrated circuits, comprising:

a source configured to generate programming data, said source being external to said integrated circuits;

a second source to generate a clock signal, said second source being external to said integrated circuits;

a first PLD device configured to receive said programming data and said clock signal, said first PLD device further configured to use said clock signal to clock said programming data to program said first PLD device to a first logic state, said first PLD device further including a done circuit which is configured to generate a done signal when said first PLD device is programmed to said first logic state; and

a second PLD device configured to receive said done signal, and in response thereto, is further configured to receive said clock signal and said programming data to program said second PLD device to a second logic state.

2. The apparatus of claim 1, wherein said source configured to generate said programming data and said second source configured to generate said clock signal are a ROM device.

3. The apparatus of claim 1, wherein said programming data and said clock signal are synchronized.

4. The apparatus of claim 1, further comprising a data bus coupled between said programming data source and said first PLD device.

5. The apparatus of claim 4, wherein said data bus is further coupled between said programming data source and said second PLD device.

6. The apparatus of claim 1, wherein said first PLD device further includes a program enable input that is configured to be tied to a first input level to assure that said first PLD device is configured to be programmed.

7. The apparatus of claim 1, wherein said first PLD device is responsive to a configuration signal by preparing itself to be re-programmed by said source configured to generate programming data.

8. The method of programming a programmable logic integrated circuit device from separate programming circuitry which includes programming data memory and a single clock signal circuit that is programmable to produce a clock signal having any of a plurality of frequencies, each frequency being suitable for use as a programming clock signal frequency by different ones of said programmable logic integrated circuit device, said method comprising:

determining a one of said frequencies that is suitable for use as a programming clock signal frequency by said programmable logic integrated circuit device;

programming said single clock signal circuit to produce said clock signal with said one of said frequencies; and

applying programming data from said programming data memory to said programmable logic integrated circuit device in synchronism with said clock signal produced by said clock signal circuit at said one of said frequencies.

9. The method defined in claim 8 wherein said applying comprises:

using said clock signal produced by said single clock signal circuit to retrieve programming data from said programming data memory at said one of said frequencies.

10. The method defined in claim 8 wherein said applying comprises:

applying said clock signal produced by said single clock signal circuit to said programmable logic integrated circuit device as a programming clock signal.

11. The method defined in claim 8 wherein said applying comprises:

applying said clock signal produced by said single clock signal circuit to said programmable logic integrated circuit in parallel with said programming data.

12. The method defined in claim 8 wherein said single clock signal circuit includes a plurality of delay elements connected in series and a plurality of programmable shunt circuits, each of which is capable of effectively removing an associated subset of said delay elements from said series by shunting said delay elements in said associated subset, said frequency of said clock signal being determined by the number of said delay elements that are effectively present in said series, and wherein said programming comprises:

programming said shunt circuits to effectively remove from said series a number of said delay elements appropriate to cause said clock signal to have said one of said frequencies.

13. Programmable logic device apparatus comprising:

a programmable logic integrated circuit device configured to be programmed by successive programming data signals applied to said device in synchronism with a programming clock signal having one of a plurality of different frequencies at which different such programmable logic integrated circuit devices can be similarly programmed by said same programming data; and

programming circuitry separate from said device and including a programming data memory and a single clock circuit, said single clock circuit being programmable to produce a programming clock signal having any one of said plurality of different frequencies, said single clock circuit being configured to apply programming data from said programming data memory to said device as programming data signals synchronized with said programming clock signal produced by said single clock circuit with said one of said frequencies.

14. The apparatus defined in claim 13 wherein said single clock circuit is further configured to retrieve programming data from said memory at said one of said frequencies.

15. The apparatus defined in claim 13 further comprising:

a first connection between said programming circuitry and said device configured to apply said programming clock signal produced by said single clock circuit to said device.

16. The apparatus defined in claim 15 further comprising:

a second connection between said programming circuit and said device configured to apply said programming data signals to said device in parallel with said programming clock signal applied to said device via said first connection.

17. The apparatus defined in claim 13 wherein said single clock circuit comprises:

a plurality of delay elements connected in series; and

a plurality of programmable shunt circuits, each of which is capable of effectively removing an associated subset of said delay elements from said series by shunting said delay elements in said associated subset, said frequency of said programming clock signal being determined by the number of delay elements that are selectively present in said series.