Radio frequency data communications device

• US 6,384,648 B1
• Filed: 04/14/2000
• Issued: 05/07/2002
• Est. Priority Date: 05/13/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ovard, David K., Tuttle, John R., Rotzoll, Robert R., Tuttle, Mark E., Lowrey, Tyler, Higgins, Brian P., Yu, Shu-Sun, Devereaux, Kevin M., Pax, George E., OʼToole, James E.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/550,647
• Time in Patent Office: 753 Days
• Field of Search: 327/155, 327/156, 327/158, 327/159, 331/1.A, 331/17, 331/34, 331/48, 331/57
• US Class Current: 327/156
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0712 the arrangement being capable of triggering distinct operating modes or functions dependent on the strength of an energy or interrogation field in the proximity of the record carrier active means for hindering electromagnetic reading or writing G06K19/07336
• CPC Class Codes: G06K 19/0716 at least one of the integrated circuit chips comprising a sensor or an interface to a sensor
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/0726 the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07758 arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10059 transponder driven
• CPC Class Codes: H01Q 1/2225 used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/148 said digital means comprising a counter or a divider

Abstract

A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Claims

1. A frequency lock loop comprising:

a current controlled oscillator including a plurality of selectively engageable current mirrors, the frequency lock loop, in operation, oscillating at an oscillation frequency, the oscillation frequency varying in response to which of the selectively engageable current mirrors are engaged, the current mirrors, in operation, including transistors configured to operate in a subthreshold mode.

2. A frequency lock loop in accordance with claim 1 and further comprising a current source including a thermal voltage generator, and wherein the selected current mirrors, in operation, multiply the current from the current source to a current to control the frequency of oscillation.

3. A frequency lock loop in accordance with claim 1 wherein the current mirrors are arranged in selectable groups of varying numbers of transistors to define a binary weighting scheme.

4. A frequency lock loop in accordance with claim 3 and further comprising digital select lines, and wherein the groups are selected by signals on the digital select lines.

5. A frequency lock loop in accordance with claim 2 wherein the thermal voltage generator has an output, wherein the frequency lock loop further comprises a resistor coupled to the output of the thermal voltage generator.

6. An integrated circuit comprising a receiver, a transmitter, and a frequency lock loop configured to supply clock signals to the receiver and transmitter, the frequency lock loop including a current source having a thermal voltage generator, a current controlled oscillator having a plurality of selectively engageable current mirrors configured to multiply up the current of the current source, the frequency of the frequency lock loop being determined based on which of the selectively engageable current mirrors are selected, the current mirrors including transistors operating in a subthreshold mode.

7. A frequency lock loop in accordance with claim 6 wherein the current mirrors are arranged in selectable groups of varying numbers of transistors to define a binary weighting scheme.

8. A frequency lock loop in accordance with claim 7 and further comprising digital select lines, and wherein the groups are selected by signals on the digital select lines.

9. A method of constructing a frequency lock loop including a current controlled oscillator having a plurality of selectively engageable current mirrors, the frequency lock loop, in operation, oscillating at an oscillation frequency, the oscillation frequency varying in response to which of the selectively engageable current mirrors are engaged, the current mirrors including transistors configured to operate in subthreshold mode.

10. A method in accordance with claim 9 and further comprising arranging the current mirrors so the engaged current mirrors multiply up current from a current source to a current for controlling the frequency of oscillation.

11. A method in accordance with claim 9 and further comprising selecting current mirrors.

12. A method in accordance with claim 9 and further comprising arranging the current mirrors in selectable groups of varying numbers of transistors to define a binary weighting gcheme.

13. A method in accordance with claim 12 and further comprising selecting the groups using digital signals.

14. A method in accordance with claim 9 wherein the current source is formed by coupling an output of the thermal voltage generator to one or more resistors.

15. A method of operating an integrated circuit including a receiver, a transmitter, and a frequency lock loop configured to supply clock signals to the receiver and transmitter, the frequency lock loop including a current source having a thermal voltage generator, a current controlled oscillator having a plurality of selectively engageable current mirrors configured to multiply up the current of the current source, the frequency of oscillation of the frequency lock loop being determined based on which of the selectively engageable current mirrors are selected, the method comprising engaging selected current mirrors and operating transistors in the current mirrors in a subthreshold mode.

16. A method in accordance with claim 15 and further comprising arranging the current mirrors in selectable groups of varying numbers of transistors to define a binary weighting scheme.

17. A method in accordance with claim 16 and further comprising selecting the groups using signals on digital select lines.

18. A method in accordance with claim 15 wherein the current source is formed by coupling an output of the thermal voltage generator to one or more resistors.