Differencing non-overlapped dual-output amplifier circuit

• US 6,384,675 B1
• Filed: 03/22/2000
• Issued: 05/07/2002
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Ang, Michael Anthony, Taylor, Alexander Dougald
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): NGUYEN, MINH T
• Application Number:
  US09/532,925
• Time in Patent Office: 776 Days
• Field of Search: 327/560-563, 327/565, 327/566, 327/108, 327/112, 327/333, 330/251-253, 330/255, 330/262-265, 330/269, 330/277, 330/301
• US Class Current: 327/562
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence

Abstract

An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines. The structures and methods are useful on a power supply board to attenuate periodic ripple voltages produced by a DC-DC converter. In general, the structures and methods are applicable in any application with a period ripple voltage.

Claims

1. A digital offset, non-overlapped, dual-output amplifier circuit comprising:

a first power supply input line;

a second power supply input line;

an amplifier input line;

a predriver stage connected to said first and second power supply input lines, and having only a single predriver stage input line wherein said single predriver state input line is connected to said amplifier input line; and

an output stage coupled to said predriver stage to receive an output signal of said predriver stage, and having;

a first output terminal of said output stage;

a second output terminal of said output stage;

wherein in a quiescent state, a first output signal on said first output terminal has a first level; and

a second output signal on said second output terminal has a second level wherein said second level is offset from said first level;

said first and second output signals swing to a third level different from said first and second levels, in response to said output signal of said predriver stage, but reach said third level at different points in time so that said first and second output signals are offset and non-overlapping for a period of time during said swing;

said digital offset, non-overlapped, dual-output amplifier circuit is self-biasing and offset-nulling; and

said predriver stage further comprises a quasi-cascode predriver, wherein said quasi-cascode predriver further comprises;

a MOSFET of a first type having;

a first lead connected to said first power supply input line;

a second lead;

a gate connected to said predriver stage input line;

a MOSFET of a second type having;

a first lead connected to said second power supply input line;

a second lead coupled to said second lead of said MOSFET of said first type;

a gate connected to said predriver stage input line; and

a predriver output line coupled to said second leads of said MOSFETS of said first and second types.

2. A digital offset, non-overlapped, dual-output amplifier circuit comprising:

a first power supply input line;

a second power supply input line;

an amplifier input line;

a predriver stage connected to said first and second power supply input lines and to said amplifier input line,

wherein said predriver stage further comprises an offset dual-output driver comprising;

a MOSFET of a first type having;

a first lead connected to said first power supply input line;

a second lead;

a gate connected to said amplifier input line;

a MOSFET of a second type having;

a first lead connected to said second power supply input line;

a second lead coupled to said second lead of said MOSFET of said first type;

a gate connected to said amplifier input line;

a first voltage divider connected between said second leads of said MOSFETS of said first and second types;

a second voltage divider connected between said second leads of said MOSFETS of said first and second types;

a first predriver output line connected to a tap of said first voltage divider; and

a second predriver output line connected to a tap of said second voltage divider; and

an output stage coupled to said predriver stage to receive an output signal of said predriver stage, and having;

a first output terminal of said output stage;

a second output terminal of said output stage;

wherein in a quiescent state, a first output signal on said first output terminal has a first level; and

a second output signal on said second output terminal has a second level wherein said second level is offset from said first level;

said first and second output signals swing to a third level different from said first and second levels, in response to said output signal of said predriver stage, but reach said third level at different points in time so that said first and second output signals are offset and non-overlapping for a period of time during said swing; and

said digital offset, non-overlapped, dual-output amplifier circuit is self-biasing and offset-nulling.

3. A digital offset, non-overlapped, dual-output amplifier circuit as in claim 2 wherein said output stage further comprises a quasi-class A push-pull driver.

4. A digital offset, non-overlapped, dual-output amplifier circuit as in claim 3 wherein said quasi-class-A push-pull driver further comprises an offset dual-output driver.

5. A digital offset, non-overlapped, dual-output amplifier circuit comprising:

a first power supply input line;

a second power supply input line;

an amplifier input line;

a predriver stage connected to said first and second power supply input lines and to said amplifier input line; and

an output stage coupled to said predriver stage to receive an output signal of said predriver stage, and having;

a first output terminal of said output stage;

a second output terminal of said output stage

wherein said output stage comprises a quasi-class A push-pull driver further comprising an offset dual-output driver comprising;

a MOSFET of a first type having;

a first lead connected to said first power supply input line;

a second lead;

a gate connected to an output line of said predriver stage;

a MOSFET of a second type having;

a first lead connected to said second power supply input line;

a second lead coupled to said second lead of said MOSFET of said first type;

a gate connected to said output line of said predriver stage;

a variable resistance element having a first lead connected to said second lead of said MOSFET of said first type; and

a second lead connected to said second lead of said MOSFET of said second type;

a first output line connected to the second lead of said MOSFET of said first type, and to said first output terminal of said output stage; and

a second output line connected to the second lead of said MOSFET of said second type, and to said second output terminal of said output stage

wherein in a quiescent state, a first output signal on said first output terminal has a first level; and

a second output signal on said second output terminal has a second level wherein said second level is offset from said first level;

said first and second output signals swing to a third level different from said first and second levels, in response to said output signal of said predriver stage, but reach said third level at different points in time so that said first and second output signals are offset and non-overlapping for a period of time during said swing; and

said digital offset, non-overlapped, dual-output amplifier circuit is self-biasing and