Rail-to-rail amplifier with reduced GM and compensating cap

• US 6,384,679 B1
• Filed: 11/15/2000
• Issued: 05/07/2002
• Est. Priority Date: 11/15/2000
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Lorenz, Perry Scott
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/714,681
• Time in Patent Office: 538 Days
• Field of Search: 330/51, 330/136, 330/285
• US Class Current: 330/51
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45717 Controlling the loading circuit of the differential amplifier

Abstract

An amplifier employs a first and second input stage amplifier, and an output stage amplifier for rail-to-rail operation. The rail-to-rail amplifier is driven by an input signal with a particular common-mode voltage. The first amplifier is active during a first range of common-mode voltages, while the second amplifier is active during a second range. A monitor circuit includes an input differential pair that operates at the same common-mode voltage as the first input differential pair in the first amplifier. The monitor circuit senses when the first amplifier has reached a condition where the amplifier begins to stop working by monitoring a current flowing in the input differential pair. The monitor circuit controls the bias current in the second amplifier'"'"'s bias circuit such that the second amplifier is enabled when the current in the monitor circuit input differential pair drops down towards zero. The outputs of the first input stage amplifier and the second input stage amplifier are coupled to the input of the output stage amplifier. Since the first and second input stage amplifiers are not on at the same time, the overall gain in the amplifier is reduced. Reducing the gain of the rail-to-rail amplifier results in a reduced size of a compensation capacitor that is coupled across the input and output of the output stage amplifier. The reduction in gain and compensation capacitor results in a lowered amount of chip space and reduced cost for the rail-to-rail amplifier.

Claims

1. An apparatus for amplifying a signal, comprising:

a first input stage amplifier;

a second input stage amplifier; and

an input amplifier monitor circuit that senses an operating state of at least one of the first and the second input stage amplifiers to produce a control signal, wherein the control signal controls one of the first and second input stage amplifiers to limit a gain of the apparatus.

2. An apparatus as in claim 1, wherein the first input stage amplifier operates over a common-mode voltage is in a first range, and the second input stage amplifier is disabled when the common-mode voltage is in the first range such that the gain of the apparatus is limited.

3. An apparatus as in claim 1, further comprising a controller circuit, wherein the controller circuit disables the second amplifier in response to the control signal when the common-mode voltage is in a first range, and the controller circuit enables the second amplifier in response to the control signal when the common-mode voltage is in a second range.

4. An apparatus as in claim 1, further comprising a controlled bias circuit having a bias output that is coupled to the second input stage amplifier.

5. An apparatus as in claim 4, wherein the controlled bias circuit selectively disables the second input stage amplifiers by disabling the bias output in response to the control signal.

6. An apparatus as in claim 1, further comprising a first differential input pair of transistors is included in the first input stage amplifier, a second differential input pair of transistors is included in the input amplifier monitor circuit, the transistors of the first differential input pair and the second differential input pair are of a same type, and the second input stage amplifier is disabled by the control signal when the second differential input pair is operating at a common-mode voltage in a first range.

7. An apparatus as in claim 6, wherein the first differential input pair of transistors and the second differential input pair of transistors share a common current source.

8. An apparatus as in claim 1, wherein the first input stage amplifier is a trans-conductance amplifier having a first output, the second input stage amplifier is a trans-conductance amplifier having a second output, and the first output and second output are coupled to a common node.

9. An apparatus as in claim 8, further comprising a compensation network that is coupled to the common node such that the gain of the apparatus is compensated by the compensation network.

10. An apparatus as in claim 8, further comprising a compensation network including a capacitor, the compensation network is coupled to the common node such that the gain of the apparatus is compensated by the compensation network, whereby a size of the capacitor in the compensation network is reduced by limiting the gain of the apparatus.

11. An apparatus as in claim 1, wherein the input amplifier monitor circuit further comprises a current sense circuit and a differential pair of transistors, the current sense circuit produces the control signal responsive to current flowing in the differential pair of transistors.

12. An apparatus as in claim 1, further comprising a bias circuit that cooperates with the input amplifier monitor circuit to produce a bias voltage for the second input stage amplifier, wherein the bias voltage disables the second input stage amplifier when the first amplifier is operating.

13. An apparatus as in claim 1, further comprising a bias circuit producing a bias voltage for the second input stage amplifier, the bias circuit including:

a first current source that generates a first current, a second current source that is controlled by the control signal to generate a second current, and a current sense circuit that senses a difference between the first current and the second current to produce the bias voltage.

14. An apparatus as in claim 1, wherein the input amplifier monitor circuit includes a current monitor circuit, wherein the current monitor circuit monitors a sample current from at least one of the first input stage amplifier and the second input stage amplifier, and the sample current is related to the control signal.

15. An apparatus as in claim 14, wherein the sample current changes as the input common-mode voltage approaches a power supply voltage, and the control signal changes when the sample current changes such that the first input stage amplifier is gradually disabled and the second input stage amplifier is gradually enabled such that the overall gain of the apparatus does not increase.

16. A method for amplifying a signal, comprising:

(a) gaining the signal with an amplifier to produce an output;

(b) gaining the signal with an other amplifier to produce an other output;

(c) combining the output with the other output to produce an other signal;

(d) amplifying the other signal to produce an amplified signal;

(e) disabling the other amplifier when the signal is in a common-mode voltage range where the amplifier is operable; and

(f) enabling the other amplifier when the signal is in an other common-mode voltage range where the amplifier is inoperable, whereby an overall gain from the signal to the amplified signal is reduced.

17. A method for amplifying a signal as in claim 16, further comprising compensating the overall gain by coupling a compensation network between the other signal and the amplified signal.

18. A method for amplifying a signal as in claim 16, wherein disabling the other amplifier further includes sensing the condition of the amplifier to produce a control signal, and disabling a bias current in the other amplifier in response to the control signal such that the other amplifier is disabled by disabling the bias current.

19. An apparatus for amplifying a signal, comprising:

(a) a first means for amplifying the signal;

(b) a second means for amplifying the signal

(c) means for sampling a current in the first means for amplifying;

(d) means for disabling the second means for amplifying when the current is in a first range; and

(e) means for enabling the second means for amplifying when the current is in a second range, whereby an overall gain in the apparatus is reduced.

20. An apparatus as in claim 19, further comprising means for limiting a gain of the apparatus, wherein the means for limiting the gain includes:

a means for compensating, the means for disabling the second means for amplifying, and the means for enabling the second means for amplifying.