Serial comparator
First Claim
1. A selectable serial comparator/shift register, in response to a selection signal, shifts serial input data or compares the serial input data with a first predetermined value and a second predetermined value, said comparator comprising:
- a) a first stage, in response to the selection signal, to selectively compare at first portion of the input serial data with the first predetermined value, or shift the input serial data; and
b) a second stage to receive a result from the first stage and, in response to the selection signal, to selectively, compare a second portion of the input serial data with the second predetermined value and to provide a comparison result of the serial data with the first and second predetermined values, or shift the input serial data.
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Accused Products
Abstract
In this invention compare circuitry is integrated into a serial shift register which can detect a bit pattern of any length with only the delay of three circuits being added to the shift of the last bit in the bit pattern. The circuitry is connected to operate either is a shift register or as a comparator for an N element bit pattern. Between adjacent registers in the shift register is a MUX used to select compare or shift register operation. An exclusive NOR circuit performs the compare between bits of the serial bit stream and reference bits of the pattern to be protected. An AND circuit accumulates the compare of a particular stage with the compare with the preceding stage. In the last stage the AND circuit provide an accumulated compare result of the preceding number of bit equaling in length the length of the bit pattern for which the compare is being performed.
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Citations
24 Claims
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1. A selectable serial comparator/shift register, in response to a selection signal, shifts serial input data or compares the serial input data with a first predetermined value and a second predetermined value, said comparator comprising:
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a) a first stage, in response to the selection signal, to selectively compare at first portion of the input serial data with the first predetermined value, or shift the input serial data; and
b) a second stage to receive a result from the first stage and, in response to the selection signal, to selectively, compare a second portion of the input serial data with the second predetermined value and to provide a comparison result of the serial data with the first and second predetermined values, or shift the input serial data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A selectable serial comparing/shift register means, in response to a selection signal, shifts serial input data or compares the serial input data with a first predetermined value and a second predetermined value, said comparing means comprising:
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a) a first circuit means, in response to the selection signal, for selectively comparing a first portion of the input serial data with the first predetermined value, or shifting the input serial data; and
b) a second circuit means for receiving a result from the first circuit means and, in response to the selection signal, for selectively comparing a second portion of the input serial data with the second predetermined value and to provide a comparison result of the serial data with the first and second predetermined values, or shifting the input serial data. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method, in response to a selection signal, of shifting serial input data or of comparing the serial input data with a first predetermined value and a second predetermined value, said method comprising the steps of:
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a) selectively, in response to the selection signal, a1) comparing a first portion of the input serial data with the first predetermined value, or a2) shifting the input serial data; and
b) selectively, response to the selection signal, b1) comparing a second portion of the input serial data with the second predetermined value and to provide a comparison result of the serial data with the first and second predetermined values, or b2) shifting the input serial data. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
c) performing logical operations on the input serial data and the first predetermined value, d) storing an output of step (c) or the input serial data in accordance with the selection signal.
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20. A method according to claim 19, wherein step (c) comprises the step of logically exclusively NORing the input data and the first predetermined data.
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21. A method according to claim 17, wherein step (b) comprises the steps of:
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c) performing logical operations on the serial data, the second predetermined value and the result from step (a), d) storing an output of said step (c) or the result from step (a) in accordance with sail selection signal.
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22. A method according to claim 21, wherein step (c) comprises the steps of:
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e) logically exclusively NORing the serial data and the second predetermined value, and f) logically ANDing all output of step (e) and the result of step (a).
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23. A method according to claim 20, wherein step (b) comprises the steps of:
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g) performing logical operations on the serial data, the second predetermined value and the result from said step (d) h) storing an output of step (g) or the result from step (d) in accordance with the selection signal.
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24. A method according to claim 23, wherein step (g) comprises the steps of:
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i) logically exclusively NORing the serial data and the second predetermined value, and j) logically ANDing an output of step (i) and the output of step (d).
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Specification