High-speed sampler structures and methods

• US 6,384,758 B1
• Filed: 11/27/2000
• Issued: 05/07/2002
• Est. Priority Date: 11/27/2000
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Nairn, David Graham, Michalski, Christopher
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/723,956
• Time in Patent Office: 526 Days
• Field of Search: 341/122, 341/156, 341/155, 341/161, 341/162, 327/91, 327/94, 327/95, 327/96, 307/353
• US Class Current: 341/122
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence

Abstract

High-speed sampler methods and structures are provided to enhance the correlation between an input signal S_in and a corresponding sampler output voltage V_out. An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor C_s is directly charged through the input buffer and the capacitor'"'"'s bottom plate to a charge that corresponds to the input signal S_in. In the holding time periods, the disabled input buffer is isolated from the sampling capacitor C_s and a common-mode signal S_cm is directly coupled to the capacitor'"'"'s bottom plate to provide the output voltage V_out at the capacitor'"'"'s top plate. Preferably, an output capacitor C_o is coupled to the sampling capacitor C_s and charge from the sampling capacitor C_s is transferred to the output capacitor C_o.

Claims

1. A method of sampling an input signal S_in and holding a corresponding output voltage V_out through successive and alternate sampling and holding time periods wherein said input signal S_in has a common-mode signal S_cm component, the method comprising the steps of:

during said sampling time periods,

a) enabling an input buffer that receives said input signal S_in; and

b) charging a sampling capacitor C_s through said input buffer to a charge that corresponds to said input signal S_in;

and during said holding time periods,

a) disabling said input buffer to thereby isolate it from said sampling capacitor C_s; and

b) coupling said sampling capacitor C_s between said common-mode signal S_cm and a sampler output port to provide said output voltage V_out.

2. The method of claim 1, wherein:

said enabling step includes the step of steering a supply current to said input buffer; and

said disabling step includes the step of steering said supply current away from said input buffer.

3. The method of claim 1, wherein said coupling step includes the step of transferring electrical charge from said sampling capacitor C_s to an output capacitor C_o.

4. The method of claim 3, wherein said transferring step includes the steps of:

connecting said output capacitor C_o between an inverting input port and an output port of a differential amplifier; and

connecting said sampling capacitor C_s between said common-mode signal S_cm and said inverting input port.

5. The method of claim 3, further including the step of discharging said output capacitor C_o during said sampling time periods.

6. A sampler for sampling an input signal S_in and holding a corresponding output voltage V_out through successive and alternate sampling and holding time periods wherein said input signal S_in has a common-mode signal S_cm component, the sampler comprising:

an input buffer that is disabled during said holding periods and that is enabled during said sampling periods to provide a version of said input signal S_in to a buffer output port of said input buffer;

a sampling capacitor C_s having a first plate that is coupled to said buffer output port and a second plate that is coupled to a sampler output port;

a charging switch S_c which enables current flow through said sampling capacitor C_s during said sampling time periods; and

a charge-transfer switch S_c-t which is open during said sampling time periods and which couples said first plate to said common-mode signal S_cm during said holding time periods;

said sampling capacitor C_s thereby charged during said sampling time periods to an electrical charge that corresponds to said input signal S_in with said second plate providing said output voltage V_out to said sampler output port during said holding time periods.

7. The sampler of claim 6, further including:

a differential amplifier having an inverting input port coupled to said second plate, a noninverting input port and an amplifier output port that forms said sampler output port; and

an output capacitor C_o that is connected between said inverting input port and said amplifier output port.

8. The sampler of claim 6, further including a current-source circuit that provides a supply current to said input buffer to enable said input buffer during said sampling time periods and removes said supply current from said input buffer to disable said input buffer during said holding time periods.

9. The sampler of claim 8, wherein said current-source circuit includes:

a current source which generates said supply current; and

a current switch which couples said supply current to said input buffer during said sampling time periods and removes said supply current from said input buffer during said holding time periods.

10. The sampler of claim 8, wherein said current-source circuit includes:

a current source which generates said supply current; and

a differential pair of first and second transistors coupled to steer said supply current to said input buffer during said sampling time periods and steer said supply current away from said input buffer during said holding time periods.

11. The sampler of claim 10, wherein said charging switch S_c, said charge-transfer switch S_c-t and said first and second transistors are metal-oxide semiconductor transistors.

12. The sampler of claim 8, wherein said current-source circuit includes a current source that provides said supply current to said input buffer during said sampling time periods and wherein said charge-transfer switch S_c-t is arranged to steer said supply current away from said input buffer during said holding time periods.

13. The sampler of claim 6, wherein said input buffer is a metal-oxide semiconductor transistor whose gate is coupled to receive said input signal S_in and whose source forms said buffer output port.

14. The sampler of claim 6, wherein said input buffer is a first bipolar junction transistor whose base is coupled to receive said input signal S_in and whose emitter forms said buffer output port and said charge-transfer switch S_c-t is a second bipolar junction semiconductor transistor that is coupled to form a differential pair with said first bipolar junction semiconductor transistor.

15. The sampler of claim 6, further including a discharge switch S_d arranged to discharge said output capacitor C_o during said sampling time periods.

16. An ananalog-to-digital converter system that converts an input signal S_in having a common-mode signal S_cm component to a corresponding digital output signal, comprising:

a sampler that is arranged to sample said input signal S_in and hold a corresponding output voltage V_out through successive and alternate sampling and holding time periods, said sampler including;

a) an input buffer that is disabled during said holding periods and that is enabled during said sampling periods to provide a version of said input signal S_in to a buffer output port of said input buffer;

b) a sampling capacitor C_s having a first plate that is coupled to said buffer output port and a second plate that is coupled to a sampler output port;

c) a charging switch S_c which enables current flow through said sampling capacitor C_s during said sampling time periods; and

d) a charge-transfer switch S_c-t which is open during said sampling time periods and which couples said first plate to said common-mode signal S_cm during said holding time periods to provide said output voltage V_out at said second plate; and

a analog-to-digital converter that converts said output voltage V_out to a respective set of digital bits of said digital output signal.

17. The system of claim 16, wherein said sampler further includes a current-source circuit that provides a supply current to said input buffer to enable said input buffer during said sampling time periods and removes said supply current from said input buffer to disable said input buffer during said holding time periods.

18. The system of claim 16, wherein said sampler further includes:

a differential amplifier having an inverting input port coupled to said second plate, a noninverting input port and an amplifier output port that forms said system output port; and

an output capacitor C_o that is connected between said inverting input port and said amplifier output port.

19. The system of claim 17, wherein said sampler further includes a discharge switch S_d arranged to discharge said output capacitor C_o during said sampling time periods.

20. The system of claim 16, wherein said analog-to-digital converter includes:

an initial analog-to-digital converter that converts said output voltage V_out to an initial set of digital bits of said digital output signal;

a digital-to-analog converter that converts said initial set of digital bits to an analog signal that is subtracted from said input signal S_in to form an analog residue signal; and

an final analog-to-digital converter that converts said analog residue signal to a final set of digital bits of said digital output signal.