Electrostatic discharge (ESD) protection circuit

• US 6,385,021 B1
• Filed: 04/10/2000
• Issued: 05/07/2002
• Est. Priority Date: 04/10/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Takeda, Fujio, Miller, James W.
• Primary Examiner(s): HUYNH, KIM NGOC
• Application Number:
  US09/546,601
• Time in Patent Office: 757 Days
• Field of Search: 361/54, 361/56, 361/111, 257/355.363, 327/306, 327/309, 327/310, 327/311, 327/318
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An ESD protection circuit (39) coupled to each of a plurality of I/O circuits (30, 32, 36) of an integrated circuit (31) is disclosed. The ESD protection circuit includes a MOSFET transistor (40) to provide primary ESD protection on occurrence of an ESD event. In one embodiment, the control electrode of the MOSFET transistor is coupled to a first buffer circuit (42). Integrated circuit (31) includes a remote trigger circuit (37) coupled to the ESD protection circuits via a trigger bus (47). The individual ESD protection circuits operate in parallel to provide ESD protection to the I/O circuits (30, 32, and 36) upon occurrence of an ESD event.

Claims

1. An integrated circuit having a VSS power supply bus and an Electrostatic Discharge (ESD) bus, comprising:

a plurality of input/output (I/O) pads coupled to the ESD bus and the VSS power supply bus; and

a plurality of individual transistors, wherein;

each individual transistor is coupled to a corresponding I/O pad; and

the plurality of individual transistors operate in parallel in response to an ESD event on at least one of the plurality of I/O pads to provide ESD protection for the plurality of I/O pads.

2. The integrated circuit of claim 1, wherein each of the plurality of individual transistors includes a first current electrode, a second current electrode, and a control electrode, and wherein the first current electrode is coupled to the ESD bus, and the second current electrode is coupled to the VSS power supply bus.

3. The integrated circuit of claim 2, further comprising a remote trigger circuit having a first terminal coupled to the ESD bus and a second terminal coupled to each of the control electrodes of the plurality of individual transistors via a trigger bus.

4. The integrated circuit of claim 3, wherein the remote trigger circuit is located at one of a power supply pad, a cell between two power supply pads, a cell between two I/O pads, and a cell between a power supply pad and an I/O pad.

5. The integrated circuit of claim 3, wherein at least one of the purality of distributed transistors if located adjacent to a power supply pad.

6. The integrated circuit of claim 3, wherein the integrated circuit further comprises a buffer circuit coupled between the trigger bus and the second terminal of the remote trigger circuit.

7. The integrated circuit of claim 3, further comprising a plurality of buffer circuits, wherein each of the plurality of buffer circuits is coupled between the trigger bus and the control electrode of at least one of the plurality of individual transistors.

8. The integrated circuit of claim 7, wherein the remote trigger circuit further comprises a remote buffer circuit coupled between the trigger bus and the second terminal of the remote trigger circuit.

9. The integrated circuit of claim 3, wherein the remote trigger circuit comprises a first capacitive element and a first resistive element, wherein:

a first terminal of the first resistive element is coupled to the ESD bus,

a second terminal of the first resistive element is coupled to the second terminal of the remote trigger circuit and a first terminal of the first capacitive element, and

a second terminal of the first capacitive element is coupled to the VSS power supply bus.

10. The integrated circuit of claim 9, further comprising a plurality of capacitive elements, wherein each capacitive element of the plurality of capacitive elements has a first terminal coupled to the control electrode of at least one of the plurality of individual transistors and a second terminal coupled to the VSS power supply bus.

11. The integrated circuit of claim 3, further comprising a plurality of capacitive elements, wherein each capacitive element of the plurality of capacitive elements has a first terminal coupled to the control electrode of at least one of the plurality of individual transistors and a second terminal coupled to the VSS power supply bus.

12. The integrated circuit of claim 1, wherein each of the individual transistors is an N-channel MOS transistor.

13. The integrated circuit of claim 12, wherein the N-channel MOS transistor has a corresponding gate size of at most approximately 300 microns and a corresponding channel length of at most approximately 0.6 microns.

14. The integrated circuit of claim 1, wherein the plurality of individual transistors provide a primary discharge path upon occurrence of the ESD event.

15. A distributed transistor circuit for Electrostatic Discharge (ESD) protection having a VSS power supply bus and an Electrostatic Discharge (ESD) bus, comprising:

a plurality of input/output (I/O) circuits coupled to the ESD bus and the VSS power supply bus;

a plurality of distributed transistors, wherein;

each of the plurality of I/O circuits includes one of the plurality of distributed transistors, and

each distributed transistor has a first current electrode coupled to the ESD bus, a second current electrode coupled to the VSS bus, and a control electrode; and

a trigger circuit corresponding to the plurality of distributed transistors, having a first terminal coupled to the ESD bus, and a second terminal coupled to each of the control electrodes of the distributed transistors via a trigger bus.

16. The circuit of claim 15, further comprising a plurality of buffer circuits wherein each buffer circuit is coupled between the control electrode of a corresponding distributed transistor and the trigger bus.

17. The circuit of claim 15, wherein the I/O circuit further comprises an output buffer coupled to the ESD bus and the VSS power supply bus.

18. The circuit of claim 15, further comprising a plurality of capacitive elements, wherein each capacitive element of the plurality of capacitive elements has a first terminal coupled to the control electrode of at least one of the plurality of distributed transistors and a second terminal coupled to the VSS power supply bus.

19. The circuit of claim 15, wherein the trigger circuit is a remote trigger circuit located at one of a power supply pad, a cell between two power supply pads, a cell between two I/O circuits, and a cell between a power supply pad and an I/O circuit.

20. The circuit of claim 15, wherein each of the distributed transistors is an N-channel MOS transistor.

21. The circuit of claim 20, wherein the N-channel MOS transistor has a corresponding gate size of at most approximately 300 microns and a corresponding channel length of at most approximately 0.6 microns.

22. The circuit of claim 15, wherein the plurality of distributed transistors operate in parallel and provide ESD protection through a primary discharge path upon occurrence of an ESD event.