Integrated circuit structure including three-dimensional memory array
First Claim
1. An integrated circuit device comprising:
- a three-dimensional array of memory cells; and
array terminal circuitry coupled to the memory array for providing to at least one selected memory cell of the array a read voltage to read the at least one selected memory cell and a write voltage to write the at least one selected memory cell; and
a voltage generator circuit to generate the write voltage.
13 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.
230 Citations
51 Claims
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1. An integrated circuit device comprising:
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a three-dimensional array of memory cells; and
array terminal circuitry coupled to the memory array for providing to at least one selected memory cell of the array a read voltage to read the at least one selected memory cell and a write voltage to write the at least one selected memory cell; and
a voltage generator circuit to generate the write voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
the memory cells comprise non-volatile memory cells; and
the integrated circuit device includes a semiconductor package which is arranged to prevent erasure of memory cells by a user thereof, even if the memory cells are fundamentally erasable.
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7. The integrated circuit device as recited in claim 1 wherein:
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the memory cells comprise non-volatile memory cells; and
the integrated circuit device includes a semiconductor package which is arranged to prevent additional programming of memory cells by a user thereof.
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8. The integrated circuit device as recited in claim 1 wherein:
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the memory cells comprise non-volatile memory cells; and
the integrated circuit device includes a write-protect capability which, when enabled, prevents erasure of memory cells by a user thereof, even if the memory cells are fundamentally erasable.
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9. The integrated circuit device as recited in claim 1 wherein:
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the memory cells comprise non-volatile memory cells; and
the integrated circuit device includes a write-protect capability which, when enabled, prevents additional programming of memory cells by a user thereof.
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10. The integrated circuit device as recited in claim 1 wherein:
each of the memory cells comprises a non-volatile two-terminal memory cell.
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11. The integrated circuit device as recited in claim 1 wherein:
each of the memory cells comprises a non-volatile three-terminal memory cell.
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12. The integrated circuit device as recited in claim 1 wherein:
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the memory cells comprise non-volatile, write-once memory cells; and
each of the memory cells comprises a two-terminal antifuse memory cell.
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13. The integrated circuit device as recited in claim 1 wherein:
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the memory cells comprise non-volatile, write-once memory cells; and
each of the memory cells comprises a two-terminal fuse memory cell.
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14. The integrated circuit device as recited in claim 1 wherein:
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the integrated circuit device is arranged to operably receive an externally-provided power supply voltage; and
at least one of the read and write voltages is greater than the power supply voltage.
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15. The integrated circuit device as recited in claim 14 wherein:
neither the read voltage nor the write voltage is substantially equal to the power supply voltage.
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16. The integrated circuit device as recited in claim 14 wherein:
the voltage generator circuit is arranged to operably receive the externally-provided power supply voltage and to generate the write voltage at a magnitude greater than the power supply voltage.
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17. The integrated circuit device as recited in claim 16 wherein the voltage generator circuit comprises a capacitive voltage multiplier circuit.
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18. The integrated circuit device as recited in claim 16 wherein the voltage generator circuit comprises an inductive voltage transformation circuit.
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19. The integrated circuit device as recited in claim 16 wherein the voltage generator circuit is arranged such that at least a portion thereof is physically disposed beneath the memory array.
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20. The integrated circuit device as recited in claim 19 wherein the at least a portion of the voltage generator circuit physically disposed beneath the memory array includes circuit structures formed within a semiconductor substrate.
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21. The integrated circuit device as recited in claim 16 wherein the voltage generator circuit is arranged such that at least a portion thereof is physically disposed above the memory array.
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22. An integrated circuit arranged to operably receive an externally-provided power supply voltage comprising:
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a three-dimensional array of non-volatile memory cells, the array having at least more than one layer of word lines or more than one layer of bit lines;
array terminal circuitry coupled to the memory array for providing to at least one selected memory cell a read voltage to read the at least one selected memory cell and a write voltage different from the read voltage to write the at least one selected memory cell, the write voltage being greater than the externally-provided power supply voltage; and
a voltage generator circuit arranged to operably receive the externally-provided power supply voltage and to generate the write voltage. - View Dependent Claims (23, 24, 25)
the memory cells comprise write-once memory cells; and
each of the memory cells comprises a two-terminal antifuse memory cell.
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24. The integrated circuit as recited in claim 22 wherein the voltage generator circuit comprises a capacitive voltage multiplier circuit arranged such that at least a portion thereof is physically disposed beneath the memory array.
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25. The integrated circuit as recited in claim 22 wherein:
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each of the memory cells comprises a write-once, two-terminal, antifuse memory cell; and
the voltage generator circuit comprises a capacitive voltage multiplier circuit arranged such that at least a portion thereof is physically disposed beneath the memory array.
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26. An integrated circuit comprising,:
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an array of memory cells; and
a voltage generator circuit arranged to operably receive an externally-provided power supply voltage and to generate a write voltage for the array;
wherein at least a portion of the voltage generator circuit is physically disposed within a lateral extent of the memory array. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35)
the memory array comprises a three-dimensional memory array.
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35. The integrated circuit as recited in claim 26 wherein:
the memory array comprises a three-dimensional memory array having at least two layers of word lines and at least two layers of bit lines.
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36. An integrated circuit device comprising:
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a three-dimensional array of non-volatile memory cells; and
a write-protect capability which, when enabled, prevents alteration of memory cells by a user thereof, even if the memory cells are fundamentally erasable. - View Dependent Claims (37, 38, 39, 40)
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41. An integrated circuit device arranged to operably receive an externally-provided power supply voltage, said integrated circuit device comprising:
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a three-dimensional array of memory cells; and
array terminal circuitry coupled to the memory array for providing to at least one selected memory cell of the array a read voltage to read the at least one selected memory cell and a write voltage different from the read voltage to write the at least one selected memory cell, at least one of the read and write voltages being greater than the externally-provided power supply voltage. - View Dependent Claims (42)
neither the read voltage nor the write voltage is substantially equal to the externally-provided power supply voltage.
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43. An integrated circuit device comprising:
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a three-dimensional array of memory cells;
array terminal circuitry coupled to the memory array for providing, to at least one selected memory cell of the array a read voltage to read the at least one selected memory cell and a write voltage different from the read voltage to write the at least one selected memory cell; and
a voltage generator circuit arranged to operably receive an externally-provided power supply voltage and to generate the write voltage at a magnitude greater than the externally-provided power supply voltage. - View Dependent Claims (44, 45)
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46. An integrated circuit device comprising:
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a three-dimensional array of memory cells;
array terminal circuitry coupled to the memory array for providing to at least one selected memory cell of the array a read voltage to read the at least one selected memory cell and a write voltage different from the read voltage to write the at least one selected memory cell; and
a voltage generator circuit arranged to operably receive an externally-provided power supply voltage and to generate the write voltage at a magnitude greater than the externally-provided power supply voltage, at least a portion of the voltage generator circuit being physically disposed beneath the memory array. - View Dependent Claims (47, 48)
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49. An integrated circuit comprising:
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an array of memory cells; and
a voltage generator circuit arranged to operably receive an externally-provided power supply voltage and to generate a write voltage for the array;
wherein at least a portion of the voltage generator circuit is physically disposed in a semiconductor layer above the memory array. - View Dependent Claims (50, 51)
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Specification