Reference signal generation for magnetic random access memory devices

• US 6,385,111 B2
• Filed: 03/14/2001
• Issued: 05/07/2002
• Est. Priority Date: 06/20/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Eldredge, Kenneth J., Tran, Lung T.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): Phung, Anh
• Application Number:
  US09/809,707
• Publication Number:
  US 20010053104A1
• Time in Patent Office: 419 Days
• Field of Search: 365/210, 365/158, 365/209, 365/207, 365/171, 365/173
• US Class Current: 365/210.12
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Claims

1. Apparatus for generating a reference signal for a block of memory cells in an MRAM device, the MRAM device including a plurality of word lines crossing rows of the memory cells and a plurality of bit lines crossing columns of memory cells, the apparatus comprising:

a first group of reference cells local to the memory cell block, each reference cell in the first group storing a first logic value;

a second group of reference cells local to the memory cell block, each reference cell in the second group storing a second logic value, the first and second logic values being different; and

a circuit for generating a reference signal for the memory cell block during a read operation, the circuit generating the reference signal by combining outputs of the first and second groups of reference cells.

2. The apparatus of claim 1, wherein the first group includes a first column of first reference cells and the second group includes a second column of second reference cells;

wherein each memory cell in the block is crossed by a word line, each word line also crossing a first reference cell in the first reference cell group and a second reference cell in the second reference cell column;

whereby selecting a word line results in a corresponding pair of first and second reference cells being selected.

3. The apparatus of claim 1, wherein the first group includes a first reference cell for storing a logic ‘

1’ and

the second group includes a second reference cell for storing a logic ‘

0’

, wherein the first and second reference cells are connected in series by a trace; and

wherein the apparatus further an amplifier coupled to trace, an output of the amplifier providing the reference signal.

4. Apparatus for generating a reference signal for a block of memory cells in an MRAM device, the MRAM device including a steering circuit and a sense amplifier for the memory cell block, the apparatus comprising:

a first storage device;

a second storage device coupled to a reference input of the sense amplifier;

a plurality of switches for coupling the first and second storage devices together and coupling the first storage device to an output of the steering circuit, and

control logic for controlling the switches to connect the first storage device to the steering circuit output during a first time interval, connect the second storage device to the steering circuit output during a second time interval, and equalize values stored in the first and second storage devices during a third time interval.

5. The apparatus of claim 4, wherein the plurality of switches includes a first switch coupled between the first storage device and a steering circuit output, and a second switch coupled between the second storage device and the first storage device;

and wherein the control logic closes the first and second switches during the first time interval, closes only the first switch during the second time interval, and closes only the second switch during the third time interval.

6. The apparatus of claim 4, wherein the plurality of switches includes a first switch coupled between the first storage device and a steering circuit output, a second switch coupled between the second storage device and the steering circuit output, and a third switch coupled between the first storage device and the second storage device;

and wherein the control logic closes the first and second switches during the first time interval, closes only the first switch during the second time interval, and closes only the second switch during the third time interval.

7. The apparatus of claim 4, further comprising a write circuit for writing a first logic value to a selected memory cell prior to the first time interval and writing a second logic value to the selected memory cell between the first and second time intervals.

8. A method of generating a reference signal for a block of memory cells in an MRAM device, the method comprising the steps of:

causing a first signal to flow through a first memory cell of the block, the first memory cell storing a first logic value;

causing a second signal to flow through a second memory cell of the block, the second memory cell storing a second logic value, the first and second logic values being different; and

combining the first and second signals to provide the reference signal.

9. A method of reading a first memory cell of a memory cell block in an MRAM device, the method comprising the steps of:

causing a sense signal to flow through the first memory cell;

causing a first signal to flow through a second memory cell of the block, the second memory cell storing a first logic value;

causing a second signal to flow through a third memory cell of the block, the third memory cell storing a second logic value, the first and second logic values being different;

combining the first and second signals to provide a reference signal; and

comparing the reference signal to the sense signal to determine whether the first or second logic value was stored in the first memory cell.

10. A method of generating a reference signal for a memory cell block in an MRAM device, the method comprising the steps of:

writing a first logic value to a memory cell in the block;

causing a first sense current to flow through the memory cell;

storing a value representing the first sense current;

writing a second logic value to the memory cell, the first and second logic values being different;

causing a second sense current to flow through the memory cell;

storing a value representing the second sense current; and

taking an average of the values representing the first and second sense currents, the average being the reference signal.

11. A method of reading a memory cell of a memory cell block in an MRAM device, the method comprising the steps of:

causing a first sense current to flow through the memory cell;

storing a first value representing the first sense current;

writing a first logic value to the memory cell;

causing a second sense current to flow through the memory cell;

storing a second value representing the second sense current;

writing a second logic value to the memory cell, the first and second logic values being different;

causing a third sense current to flow through the memory cell;

storing a third value representing the third sense current;

taking an average of the second and third values; and

comparing the first value to the average.