Differential charge pump

• US 6,385,265 B1
• Filed: 08/04/1998
• Issued: 05/07/2002
• Est. Priority Date: 08/04/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moyal, Nathan Y., Duffy, Michael L., Williams, Bertrand J., Kruczkowski, Phillip J., Prakash, Jaideep
• Primary Examiner(s): Corrielus, Jean
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/128,901
• Time in Patent Office: 1,372 Days
• Field of Search: 375/374, 375/375, 375/376, 375/377, 375/226, 326/136, 326/82, 326/99, 326/96, 327/148, 327/147, 327/150, 327/157, 327/159, 327/536, 327/537, 327/563, 331/8, 331/10, 331/25
• US Class Current: 375/374
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses

Abstract

A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

Claims

1. A circuit comprising:

a charge pump configured to generate a first and a second output signal in response to (a) a first differential element comprising (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal and (b) a second differential element comprising (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive said first and a second control signals, wherein (i) said first unity gain buffer has an input configured to receive said first output signal and an output coupled to drains/sources of said first and second transistor pairs and (ii) said second unity gain buffer has an input configured to receive said second output signal and an output coupled to drains/sources of said third and fourth transistor pairs.

2. The circuit according to claim 1, wherein said first control signal comprises a first differential input and said second control signal comprises a second differential input.

3. The circuit according to claim 1, wherein:

said first control signal comprises a first differential portion that is a digital complement of a second differential portion; and

said second control signal comprises a first differential portion that is a digital complement of a second differential portion.

4. The circuit according to claim 2, further comprising:

a voltage controlled oscillator configured to present a third output in response to said first and a second differential inputs.

5. The circuit according to claim 1, wherein said charge pump is configured to present said first and said second output signals in further response to one or more bias signals.

6. The circuit according to claim 5, further comprising:

a control circuit configured to present one of said bias signals in response to (i) another one of said bias signals and (ii) said first and second output signals.

7. The circuit according to claim 4, further comprising:

a phase detector configured to present said control signals in response to (i) a data input signal and (ii) said third output signal.

8. The circuit according to claim 1, further comprising a loop filter.

9. The circuit according to claim 5, wherein said first differential element presents said first tput signal and said second differential element presents said second output signal.

10. The circuit according to claim 9, wherein said first and second differential elements present said first and second output signals in response to said bias signals.

11. A circuit comprising:

means for generating a first and a second output signal comprising a charge pump having (a) a first differential element comprising (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and a second control signal and (b) a second differential element comprising (i) a second unity gain buffer and (ii) a third and a fourth pair of transistors configured to receive said first and second control signals, wherein (i) said first unity gain buffer has an input configured to receive said first output signal and an output coupled to drains/sources of said first and second transistor pairs and (ii) said second unity gain buffer has an input configured to receive said second output signal and an output coupled to drains/sources of said third and fourth transistor pairs.

12. A method for generating a first and a second output signal comprising:

(A) generating said first output signal in response to (a) a first differential element comprising (i) a first unity gain buffer and (ii) a first and a second transistor pair; and

(B) generating said second output signal in response to a second differential element comprising (i) a second unity gain buffer and (ii) a third and a fourth transistor pair, wherein (i) said first unity gain buffer has an input configured to receive said first output signal and an output coupled to drains/sources of said first and said second transistor pairs and (ii) said second unity gain buffer has an input configured to receive said second output signal and an output coupled to drains/sources of said third and said fourth transistor pairs.

13. The method according to claim 12, wherein step (A) generates said first output in further response to a first and a second control signal.

14. The method according to claim 13, wherein said first control signal comprises a differential input and said second control signal comprises a second differential input.

15. The method according to claim 13, wherein said first control signal comprises a first differential portion and said second control signal comprises a second differential portion that is a digital complement of said first differential portion.

16. The method according to claim 13, wherein said second control signal comprises a first differential portion and a second differential portion that is a digital complement of said first differential portion.

17. The method according to claim 14, further comprising the step of:

generating a third output in response to said first and second differential inputs.

18. The method according to claim 17, further comprising the step of:

generating said first and second control signals in response to (i) a data input signal and (ii) said third output signal.

19. The method according to claim 15, further comprising the step of:

generating said first and second control signals in further response to one or more bias signals.

20. The method according to claim 13, wherein step (B) generates said second output in further response to said first and second control signals.