Spread spectrum localizers

• US 6,385,268 B1
• Filed: 07/22/1999
• Issued: 05/07/2002
• Est. Priority Date: 07/22/1994
• Status: Expired due to Term

• Current Assignee: Zebra Technologies Corporation
• Original Assignee: Aether-Wire & Technology
• Inventors: Fleming, Robert Alan, Kushner, Cherie Elaine
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US09/359,578
• Time in Patent Office: 1,020 Days
• Field of Search: 375/377, 455/269, 343/905
• US Class Current: 375/377
• CPC Class Codes: G01S 1/026 of associated receivers
• CPC Class Codes: G01S 1/045 Receivers
• CPC Class Codes: G01S 11/02 using radio waves G01S19/00 takes precedence
• CPC Class Codes: G01S 13/876 Combination of several spaced transponders or reflectors of known location for determining the position of a receiver G01S13/874 takes precedence
• CPC Class Codes: G01S 5/0063 of measured values, i.e. measurement on base station and position calculation on mobile
• CPC Class Codes: G01S 5/0072 Transmission between mobile stations, e.g. anti-collision systems
• CPC Class Codes: G01S 5/009 Transmission of differential positioning data to mobile
• CPC Class Codes: G01S 5/14 Determining absolute distances from a plurality of spaced points of known location
• CPC Class Codes: G01S 5/145 Using a supplementary range measurement, e.g. based on pseudo-range measurements
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/709 Correlator structure

Abstract

A network of localizers determines relative locations in three-dimensional space to within 1 cm by cooperatively measuring propagation times of pseudorandom sequences of electromagnetic impulses. Ranging transmissions may include encoded digital information to increase accuracy. The propagation time is determined from a correlator circuit which provides an analog pseudo-autocorrelation function sampled at discrete time bins. The correlator has a number of integrators, each integrator providing a signal proportional to the time integral of the product of the expected pulse sequence delayed by one of the discrete time bins, and the non-delayed received antenna signal. With the impulses organized as doublets the sampled correlator output can vary considerably in shape depending on where the autocorrelation function peak falls in relation to the nearest bin. Using pattern recognition the time of arrival of the received signal can be determined to within a time much smaller than the separation between bins. Because operation of standard CMOS circuitry generates noise over a large frequency range, only low-noise circuitry operates during transmission and reception. To provide the time accuracy necessary for distancing, a high-frequency clock operates during inter-localizer communications. The high-frequency clock uses a phase-lock loop circuit to increase the clock rate and a programmable delay to provide still finer time graduations. A stage in the low-frequency clock uses low-noise circuitry during transmissions and receptions, and standard circuitry at other times.

Claims

1. An antenna circuit for transmitting rapid impulses of electromagnetic radiation comprising:

a source of current;

a current sink;

an antenna having a first lead and a second lead;

a first high speed switch connecting said source of current to said first lead;

a second high speed switch connecting said source of current to said second lead;

a third high speed switch connecting said current sink to said first lead;

a fourth high speed switch connecting said current sink to said second lead;

a first control means for closing said first high speed switch when opening said third high speed switch if said first high speed switch is open and said third high speed switch is closed, and for closing said third high speed switch when opening said first high speed switch if said third high speed switch is open and said first high speed switch is closed; and

a second control means for closing said second high speed switch when opening said fourth high speed switch if said second high speed switch is open and said fourth high speed switch is closed, and for closing said fourth high speed switch when opening said third high speed switch if said fourth high speed switch is open and said second high speed switch is closed, said second control means being independent of said first control means, current flow through said antenna being terminated by switching of said first control means and said second control to produce closure of said first high speed switch and said second high speed switch and opening of said third high speed switch and said fourth high speed switch, or closure of said third high speed switch and said fourth high speed switch and opening of said first high speed switch and said second high speed switch.

2. The antenna circuit of claim 1 further including a means for connecting said first and second leads to said source of current to insure that no current flows through said antenna.

3. The antenna circuit of claim 1 further including a means for connecting said first and second leads to said current sink to insure that no current flows through said antenna.

4. The antenna circuit of claim 1 further including a means for alternately connecting said first and second leads to said source of current and said current sink between chip transmissions to insure that no current flows through said antenna.

5. The antenna circuit of claim 1 further including a means for connecting said first and second leads to said source of current after transmission of a chip if said chip has a first polarity, and connecting said first and second leads to said current sink after transmission of said chip if said chip has a second polarity opposite said first polarity.

6. The antenna circuit of claim 1 wherein said first high speed switch includes a first p-channel CMOS transistor, said second high speed switch includes a second p-channel CMOS transistor, said third high speed switch includes a first n-channel CMOS transistor, and said fourth high speed switch includes a second n-channel CMOS transistor.

7. The antenna circuit of claim 1 wherein said first high speed switch includes a first n-channel CMOS transistor, said second high speed switch includes a second n-channel CMOS transistor, said third high speed switch includes a third n-channel CMOS transistor, and said fourth high speed switch includes a fourth n-channel CMOS transistor.

8. The antenna circuit of claim 1 wherein said first control means includes a first delay means connected to said first high speed switch and a second delay means connected to said third high speed switch, whereby the switching of said first high speed switch and said third high speed switch can be synchronized.

9. The antenna circuit of claim 8 wherein said second control means includes a third delay means connected to said second high speed switch and a fourth delay means connected to said fourth high speed switch, whereby the switching of said first, second, third and fourth high speed switches can be synchronized.

10. The antenna circuit of claim 1 wherein said antenna comprises a conducting plate, said first lead is connected to a first side of said plate, and said second lead is connected to a second side of said plate opposite said first side of said plate.

11. The antenna of claim 10 wherein said antenna is unshielded.

12. The antenna circuit of claim 1 wherein said antenna comprises a conducting plate and has third and fourth leads, said first, second, third and fourth leads being mounted on first, second, third and fourth sides of said antenna, respectively, said first side being opposite said second side, said third side being opposite said fourth side, a first direction from said first lead to said second lead being orthogonal to a second direction from said third lead to said fourth lead, further comprising:

a fifth high speed switch connecting said source of current to said third lead;

a sixth high speed switch connecting said source of current to said fourth lead;

a seventh high speed switch connecting said current sink to said third lead;

an eighth high speed switch connecting said current sink to said fourth lead;

a third control means for closing said fifth high speed switch when opening said seventh high speed switch if said fifth high speed switch is open and said seventh high speed switch is closed, or for closing said seventh high speed switch when opening said fifth high speed switch if said seventh high speed switch is open and said fifth high speed switch is closed; and

a fourth control means for closing said sixth high speed switch when opening said eighth high speed switch if said sixth high speed switch is open and said eighth high speed is closed, or for closing said eighth high speed switch when opening said sixth high speed switch if said eighth high speed switch is open and said sixth high speed switch is closed.