Method and system for controlling test data volume in deterministic test pattern generation

• US 6,385,750 B1
• Filed: 09/01/1999
• Issued: 05/07/2002
• Est. Priority Date: 09/01/1999
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Williams, Thomas W., Kapur, Rohit, Wohl, Peter, Waicukauski, John
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/387,865
• Time in Patent Office: 979 Days
• Field of Search: 714/738, 714/724
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31813 Test pattern generators

Abstract

A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T. Based on the fault propagation information, test points are selectively inserted to maximize the fault coverage of the set of test patterns, T. In one embodiment, the nets to which most untested faults propagate are selected for test point insertion. The number of test points selected may be determined by user-defined parameters. These steps are then repeated for another set of set patterns until the desired fault coverage is achieved. By adding test points, the fault coverage of the test patterns is significantly improved, thus reducing the test data volume.

Claims

1. In a computer controlled electronic design automation system, a method of improving fault coverage of test patterns for testing integrated circuits, said method comprising the steps of:

a) accessing a netlist description of an integrated circuit design comprising a plurality of logic cells intercoupled by a plurality of nets;

b) generating a plurality of test patterns for testing a first plurality of faults of said integrated circuit design;

c) fault simulating of said plurality of test patterns;

d) during said fault simulating step (c), monitoring fault propagation of a second plurality of faults that are untested by said plurality of test patterns;

e) generating fault propagation information of said second plurality of faults; and

f) based on said fault propagation information, selecting appropriate ones of said plurality of nets for test point insertion, said step (f) causing a portion of said second plurality of faults to be detectable by said plurality of test patterns.

2. A method as recited in claim 1 wherein said step (c) further comprises the steps of:

c1) recording respective ones of said plurality of nets to which said second plurality of faults propagate; and

c2) recording respective ones of said plurality of nets where propagation of said second plurality of faults discontinues.

3. A method as recited in claim 1 further comprising the step of

(g) inserting test point circuits at said appropriate ones of said plurality of nets selected at said step (f).

4. A method as recited in claim 3 wherein said test point circuits comprise an observe point circuit.

5. A method as recited in claim 3 wherein said test point circuits comprise a control point circuit.

6. A method as recited in claim 1 further comprising the step of repeating said steps (b) to (f) until a predetermined threshold of fault coverage is achieved.

7. A method as recited in claim 1 wherein a number nets selected for test point insertion by said step (f) is determined by a user-defined threshold.

8. A method as recited in claim 1 wherein said step (f) further comprises the steps of:

f1) selecting a respective one of said plurality of nets to which a predetermined threshold of said second plurality of fault propagate; and

f2) selecting said respective one of said plurality of nets for test point insertion.

9. A method as recited in claim 1 wherein said plurality of test patterns are deterministic test patterns.

10. A method as recited in claim 1 wherein said step (b) further comprises the step of compacting and merging said plurality of test patterns to further reduce test data volume.

11. In a computer controlled electronic design automation system, a method of improving fault coverage of test patterns for testing integrated circuits, said method comprising the steps of:

a) accessing a netlist description of an integrated circuit design comprising a plurality of logic cells intercoupled by a plurality of nets;

b) generating a plurality of deterministic test patterns for testing a first plurality of faults of said integrated circuit design, wherein a second plurality of faults are undetected by said plurality of deterministic test patterns; and

c) causing respective ones of said second plurality of faults to become detectable by said plurality of deterministic test patterns by selecting appropriate ones of said plurality of nets for test point insertion.

12. A method according to claim 11 wherein said step (c) comprises the steps of:

monitoring fault propagation of said second plurality of faults during fault simulation of said plurality of test patterns; and

generating fault propagation information of said second plurality of faults wherein said appropriate ones of said plurality of nets are selected based on said fault propagation information.

13. A method as recited in claim 12 wherein said step of monitoring further comprises the steps of:

recording respective ones of said plurality of nets to which said second plurality of faults propagate; and

recording respective ones of said plurality of nets where propagation of said second plurality of faults discontinues.

14. A method as recited in claim 11 wherein said step (c) further comprises the steps of:

fault simulating said plurality of deterministic test patterns;

monitoring fault propagation of said second plurality of faults during said fault simulating step and generating fault propagation information thereof;

selecting a respective one of said plurality of nets to which a predetermined number of said second plurality of faults propagate; and

selecting said respective one of said plurality of nets for test point insertion.

15. A method as recited in claim 11 further comprising the step of inserting test point circuits at said appropriate ones of said plurality of nets.

16. A method as recited in claim 15 wherein said test point circuits comprise an observe point circuit.

17. A method as recited in claim 15 wherein said test point circuits comprise a control point circuit.

18. A method as recited in claim 11 further comprising the step of repeating said steps (b) and (c) until a predetermined threshold of fault coverage is achieved.

19. A method as recited in claim 11 wherein a number nets selected for test point insertion by said step (c) is determined by a user-defined threshold.

20. A method as recited in claim 11 further comprising the step of compacting and merging said plurality of deterministic test patterns to further reduce test data volume.

21. An electronic design automation system comprising:

a processor;

a bus coupled to said processor; and

a computer readable memory coupled to said bus and having stored therein computer readable program code for causing said electronic design automation system to perform a method of improving fault coverage of test patterns for testing integrated circuits, said method comprising the steps of;

a) accessing a netlist description of an integrated circuit design that has a plurality of logic cells intercoupled by a plurality of nets;

b) generating a plurality of test patterns for testing a first plurality of faults of said integrated circuit design;

c) fault simulating said plurality of test patterns;

d) monitoring fault propagation of a second plurality of faults that are untested by said plurality of test patterns during said fault simulating step (c);

e) generating fault propagation information of said second plurality of faults; and

f) based on said fault propagation information, selecting appropriate ones of said plurality of nets for test point insertion, said step (f) causing respective ones of said second plurality of faults to become detectable by said plurality of test patterns.

22. An electronic design automation system as recited in claim 21 wherein said step (c) further comprises the steps of:

recording respective ones of said plurality of nets to which said second plurality of faults propagate; and

recording respective ones of said plurality of nets where propagation of said second plurality of faults discontinues.

23. An electronic design automation system as recited in claim 21 wherein said method further comprises the step of

(g) inserting test point circuits at said appropriate ones of said plurality of nets.

24. An electronic design automation system as recited in claim 23 wherein said test point circuits comprise an observe point circuit.

25. An electronic design automation system as recited in claim 23 wherein said test point circuits comprise a control point circuit.

26. An electronic design automation system as recited in claim 21 wherein said method further comprises the step of repeating said steps (b) to (f) until a predetermined threshold of fault coverage is achieved.

27. An electronic design automation system as recited in claim 21 wherein a number of nets selected by said step (f) is determined by a user-defined threshold.

28. An electronic design automation system as recited in claim 21 wherein said step (f) further comprises the steps of:

f1) selecting a respective one of said plurality of nets to which most of said second plurality of fault propagate; and

f2) selecting said respective one of said plurality of nets for test point insertion.

29. An electronic design automation system as recited in claim 21 wherein said set of test patterns are deterministic test patterns.

30. An electronic design automation system as recited in claim 21 wherein said method further comprises the step of compacting and merging said plurality of deterministic test patterns to further reduce test data volume.