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System and method for concurrent placement of gates and associated wiring

  • US 6,385,760 B2
  • Filed: 06/12/1998
  • Issued: 05/07/2002
  • Est. Priority Date: 06/12/1998
  • Status: Expired due to Term
First Claim
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1. A method for placing circuit elements onto a target area of a semiconductor substrate, comprising:

  • providing an initial placement of said circuit elements onto said target area, wherein during said initial placement, circuit elements are placed within bins;

    providing, for each of a plurality of selected nets interconnecting said circuit elements, a probabilistic model of interconnect wiring, said probabilistic model incorporating a metric relating a routing length and a routing area, wherein said probabilistic models are provided for interconnect wiring between circuit elements of different bins;

    providing a second placement of said circuit elements by reassigning selected ones of said circuit elements;

    updating said probabilistic model of interconnect wiring for each of said selected ones of said circuit elements, according to said second placement;

    subdividing the bins into successively smaller bins, wherein said steps of providing a second placement and adjusting the probabilistic models are repeated for said successively smaller bins; and

    when said smaller bins reach a predetermined size, transforming each of said probabilistic model into an actual interconnect wiring.

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