System and method for concurrent placement of gates and associated wiring

• US 6,385,760 B2
• Filed: 06/12/1998
• Issued: 05/07/2002
• Est. Priority Date: 06/12/1998
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Monterey Design Systems, Inc. (Synopsys Incorporated)
• Inventors: Gao, Tong, Yeap, Gary K., Taraporevala, Feroze Peshotan, Sarrafzadeh, Majid, Boyle, Douglas B., Pileggi, Lawrence
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/096,804
• Publication Number:
  US 20010047507A1
• Time in Patent Office: 1,425 Days
• Field of Search: 716/1, 716/2, 716/7, 716/8, 716/9, 716/10, 716/11, 716/12, 716/14, 716/13
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.

Claims

1. A method for placing circuit elements onto a target area of a semiconductor substrate, comprising:

providing an initial placement of said circuit elements onto said target area, wherein during said initial placement, circuit elements are placed within bins;

providing, for each of a plurality of selected nets interconnecting said circuit elements, a probabilistic model of interconnect wiring, said probabilistic model incorporating a metric relating a routing length and a routing area, wherein said probabilistic models are provided for interconnect wiring between circuit elements of different bins;

providing a second placement of said circuit elements by reassigning selected ones of said circuit elements;

updating said probabilistic model of interconnect wiring for each of said selected ones of said circuit elements, according to said second placement;

subdividing the bins into successively smaller bins, wherein said steps of providing a second placement and adjusting the probabilistic models are repeated for said successively smaller bins; and

when said smaller bins reach a predetermined size, transforming each of said probabilistic model into an actual interconnect wiring.

2. A system for placing circuit elements onto a target area of a semiconductor substrate, comprising:

a placement tool for placing an initial placement of said circuit elements onto said target area, the placement tool being configured to place said circuit elements within bins, the bins being subdivided into successively smaller bins;

means for providing, for each of a plurality of selected nets interconnecting said circuit elements, a probabilistic model of interconnect wiring, said probabilistic model incorporating a metric relating a routing length and a routing area, wherein the probabilistic models are provided for interconnect wiring between circuit elements of different bins, and wherein said placement tool, upon completion by said means for providing of said probabilistic model, provides a second placement of said circuit elements by reassigning selected ones of said circuit elements; and

thereupon, said means for providing a probabilistic model updates said probabilistic model of interconnect wiring for each of said selected ones of said circuit elements according to said second placement, said steps of providing a second placement and adjusting the probabilistic models being repeated for said successively smaller bins until, when said smaller bins reach a predetermined size, transforming each of said probabilistic model into an actual interconnect wiring.

3. A method for placing circuit elements onto a target area of a semiconductor substrate, comprising:

providing an initial placement of said circuit elements onto said target area;

providing, for each of a plurality of selected nets interconnecting said circuit elements, a probabilistic model of interconnect wiring, said probabilistic model incorporating a metric relating a routing length and a routing area, wherein said metric relates an average routing length over a predetermined number of routes having a substantially minimal interconnect delay over a routing area represented by a bounding box;

providing a second placement of said circuit elements by reassigning selected ones of said circuit elements; and

updating said probabilistic model of interconnect wiring for each of said selected ones of said circuit elements, according to said second placement.

4. A method for placing circuit elements onto a target area of a semiconductor substrate, comprising:

providing an initial placement of said circuit elements onto said target area;

providing, for each of a plurality of selected nets interconnecting said circuit elements, a probabilistic model for interconnect wiring, said probabilistic model incorporating a metric relating a routing length and a routing area, wherein said metric relates an average interconnect length over a predetermined number of routes having a substantially minimal interconnect delay over two or more bounding regions;

providing a second placement of said circuit elements by reassigning selected ones of said circuit elements; and

updating said probabilistic model of interconnect wiring for each of said selected ones of said circuit elements, according to said second placement.

5. A method as in claim 4, wherein said two or more bounding regions have different wiring densities.

6. A system for placing circuit elements onto a target area of a semiconductor substrate, comprising:

a placement tool for placing an initial placement of said circuit elements onto said target area; and

means for providing, for each of a plurality of selected nets interconnecting said circuit elements, a probabilistic model of interconnect wiring, said probabilistic model incorporating a metric relating a routing length and a routing area, wherein said metric relates an average routing length over a predetermined number of routes having a substantially minimal interconnect delay over a routing area represented by a bounding box, and wherein

said placement tool, upon completion by said means for providing of said probabilistic model, provides a second placement of said circuit elements by reassigning selected ones of said circuit elements; and

thereupon, said means for providing a probabilistic model updates said probabilistic model of interconnect wiring for each of said selected ones of said circuit elements, according to said second placement.

7. A system for placing circuit elements onto a target area of a semiconductor substrate, comprising:

a placement tool for placing an initial placement of said circuit elements onto said target area; and

means for providing, for each of a plurality of selected nets interconnecting said circuit elements, a probabilistic model of interconnect wiring, said probabilistic model incorporating a metric relating a routing length and a routing area, wherein said metric relates an average interconnect length over a predetermined number of routes having a substantially minimal interconnect delay over two or more bounding regions, and wherein

said placement tool, upon completion by said means for providing of said probabilistic model, provides a second placement of said circuit elements by reassigning selected ones of said circuit elements; and

thereupon, said means for providing a probabilistic model updates said probabilistic model of interconnect wiring for each of said selected ones of said circuit elements, according to said second placement.

8. A system as in claim 7, wherein said two or more bounding regions have different wiring densities.