Method for adhering and sealing a silicon chip in an integrated circuit package

• US 6,387,729 B2
• Filed: 07/06/2001
• Issued: 05/14/2002
• Est. Priority Date: 12/19/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Low, Siu Waf, Yee, Pak Hong, Eng, Kian Teng, Yew, Chee Kiang, Chan, Min Yu, Goh, Jing Sua, Toh, Tuck Fook, Chan, Boon Pew
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Jones, Josetta I.
• Application Number:
  US09/899,193
• Publication Number:
  US 20020001882A1
• Time in Patent Office: 312 Days
• Field of Search: 438/108, 438/118, 438/127
• US Class Current: 438/106
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/20106 : Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
• CPC Class Codes: H01L 2924/20107 : Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
• CPC Class Codes: H01L 2924/20108 : Temperature range 300 C=<T<350 C, 573.15K =<T< 623.15K
• CPC Class Codes: H01L 2924/20109 : Temperature range 350 C=<T<400 C, 623.15K =<T< 673.15K
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Claims

1. A process for fabricating an integrated circuit package comprising the steps of:

providing a substrate having an opening extending therethrough to a pair of opposing surfaces of said substrate;

placing a chip having a pair of opposing major surfaces and a perimeter within said opening in contact with said adhesive material, said chip having a least one bonding pad extending into said opening;

extending a plurality of routing strips within said substrate to said opening;

disposing a plurality of pads on a said surface of said substrate;

electrically connecting at least one of said pads with at least one of said routing strips;

electrically connecting said routing strips to said at least one bonding pad on said chip with wire bonding;

disposing an adhesive material on said substrate and within said opening opposed to said chip;

adhering said chip to said substrate with said adhesive material within said opening; and

then heating said chip and said adhesive material to provide an hermetic seal around the perimeter of said chip with said adhesive material to protect said chip; and

filling said opening with a potting material.

3. The process as recited in claim 1 further comprising the step of attaching at least one solder ball to at least one of said pads disposed on said first surface.

4. The process as recited in claim 1 wherein the step of adhering said chip to said substrate with said adhesive material further includes placing said chip on a mounting stage, applying heat to said chip and applying a force to said chip.

5. The process as recited in claim 4 wherein the step of providing a seal around the perimeter of said chip with said adhesive material further includes flowing said adhesive around the perimeter of said chip.

2. A process for fabricating an integrated circuit package comprising :

providing a substrate having an opening extending therethrough to a pair of opposing surfaces of said substrate;

placing a chip having a pair of opposing major surfaces and a perimeter within said opening in contact with said adhesive material, said chip having a least one bonding pad extending into said opening;

extending a plurality of routing strips within said substrate to said opening;

disposing a plurality of pads on a said surface of said substrate;

electrically connecting at least one of said pads with at least one of said routing strips;

electrically connecting said routing strips to said at least one bonding pad on said chip with wire bonding;

disposing an adhesive material on said substrate and within said opening opposed to said chip;

adhering said chip to said substrate with said adhesive material within said opening; and

heating said chip and said adhesive material to provide an hermetic seal around the perimeter of said chip with said adhesive to protect said chip; and

filling said opening with a potting material;

further including the steps of;

disposing at least one bus bar on said substrate;

electrically connecting said at least one bus bar with at least one of said bonding pads with wire bonding; and

electrically connecting said at least one bus bar with at least one of said pads disposed on said first surface.