Method and improved SOI body contact structure for transistors
First Claim
1. In a process for making an SOI transistor, the steps comprising:
- forming a transistor having a source, and a drain separated by a gate which has a body contact therefor formed of a poly layer for contact with said gate, and wherein a shaped field oxide opening exposing active silicon is formed with a topology which overlaps the gate structure which separates the source and the drain and which has a linear extension area over the shaped field oxide opening as well as an area normal to said lineal extension area to define the gate for said transistor with which a first gate part of the transistor is mirrored by a second mirror image gate part of the first gate part when the topology of the gate is viewed from above, whereby a misalignment in a first direction will make the transistor device width larger, while a misalignment in a second direction opposite the first direction will make the device width smaller to remove overlay tolerance from the effective transistor width, and wherein, in the process of forming said transistor device the body contract area is doped to a high concentration using the parts of the topology applicable to the gate made a diffusion mask area and making the body contact to the body under the diffusion mask area , and wherein the gate structure is formed of a pair of top-to-top “
T”
shaped elements which are laid to bound a single;
body with the area normal to the lineal extension area of each “
T”
being aligned and generally parallel to one another to bound and contact the body contact area of said transistor device.
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Accused Products
Abstract
Disclosed is process for maufacture of a type “BC” body contacted SOI transistor with a process for making these transistors in a manufacturing environment to providing a structure which removes overlay tolerance from the effective transistor width during the course of manufacture. The width is determined by RX on the top side, but by PC on the other with source and drain connected together. In the preferred embodiment such a structure is used as the top part of the SOI transistor with the bottom part a mirror image of the top part such that the effect of the PC to RX overlay is reversed, and the top part and bottom part are connected by a common body part. For the bottom part an “UP misalignment will make the device with large, while a “DOWN” misalignment will make the device width smaller. Thus, if PC is misalleged with respect to RX, any width errors introduced in the top part of the transistor will be exactly canceled by the bottom part of the transistor. An alternative DOG BONE embodiment is also illustrated which also provides a structure which removes the overlay tolerance from the effective transistor width.
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Citations
3 Claims
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1. In a process for making an SOI transistor, the steps comprising:
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forming a transistor having a source, and a drain separated by a gate which has a body contact therefor formed of a poly layer for contact with said gate, and wherein a shaped field oxide opening exposing active silicon is formed with a topology which overlaps the gate structure which separates the source and the drain and which has a linear extension area over the shaped field oxide opening as well as an area normal to said lineal extension area to define the gate for said transistor with which a first gate part of the transistor is mirrored by a second mirror image gate part of the first gate part when the topology of the gate is viewed from above, whereby a misalignment in a first direction will make the transistor device width larger, while a misalignment in a second direction opposite the first direction will make the device width smaller to remove overlay tolerance from the effective transistor width, and wherein, in the process of forming said transistor device the body contract area is doped to a high concentration using the parts of the topology applicable to the gate made a diffusion mask area and making the body contact to the body under the diffusion mask area , and wherein the gate structure is formed of a pair of top-to-top “
T”
shaped elements which are laid to bound a single;
body with the area normal to the lineal extension area of each “
T”
being aligned and generally parallel to one another to bound and contact the body contact area of said transistor device.
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2. In a process for making an SOI transistor, the steps comprising:
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forming a transistor having a source, and a drain separated by a gate which has a body contact therefor formed of a poly layer for contact with said gate, and wherein a shaped field oxide opening exposing active silicon is formed with a topology which overlaps the gate structure which separates the source and the drain and which has a linear extension area over the shaped field oxide opening as well as an area normal to said lineal extension area to define the gate for said transistor with which a first gate part of the transistor is mirrored by a second mirror image rate part of the first gate part when the topology of the gate is viewed from above, whereby a misalignment in a first direction will make the transistor device width larger, while a misalignment in a second direction opposite the first direction will make the device width smaller to remove overlay tolerance from the effective transistor width, and wherein, in the process of forming said transistor device the body contract area is doped to a high concentration using the parts of the topology applicable to the gate made a diffusion mask area and making the body contact to the body under the diffusion mask area , and wherein source and drain terminals of the transistor device have a gate formed therebetween and the gate has at both ends of the gate extensions which are substantially perpendicular to the direction of the gate, and which bound end contact a body contact at each end of the gate structure. - View Dependent Claims (3)
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Specification