Semiconductor device manufacturing method and semiconductor device

• US 6,387,743 B1
• Filed: 10/18/2001
• Issued: 05/14/2002
• Est. Priority Date: 04/19/2000
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Itoh, Yasuyoshi, Shiozawa, Katsuomi, Ueno, Syuichi
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US09/978,540
• Publication Number:
  US 20020024095A1
• Time in Patent Office: 208 Days
• Field of Search: 438/199, 438/230, 438/267, 438/366, 438/367, 438/368, 438/558, 438/567
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.

Claims

1. A semiconductor device manufacturing method, comprising the steps of:

(a) forming first and second main source/drain regions of a first conductivity type in a surface of a semiconductor substrate and a temporary gate electrode portion on said semiconductor substrate between said first and second main source/drain regions;

(b) forming first and second auxiliary side walls on sides of said temporary gate electrode portion;

(c) removing said temporary gate electrode portion to obtain an opening whose sides are defined by said first and second auxiliary side walls;

(d) forming first and second extension-forming side walls adjacent respectively to said first and second auxiliary side walls in said opening, said first and second extension-forming side walls containing a first extension-forming impurity of the first conductivity type;

(e) after said step (d), sequentially forming a first real gate insulating film and a first real gate electrode in said opening to obtain a first real gate electrode portion; and

(f) forming first and second extension regions of the first conductivity type adjacent respectively to said first and second main source/drain regions through a first diffusion process where said first extension-forming impurity in said first and second extension-forming side walls serves as a diffusion source,

wherein said first real gate insulating film, said first real gate electrode, said first and second main source/drain regions and said first and second extension regions define an insulated-gate, first transistor of the first conductivity type.

2. The semiconductor device manufacturing method according to claim 1, wherein

said step (f) includes a step of forming an interlayer insulating film all over the surface of said semiconductor substrate including said first transistor, and

said first diffusion process includes a diffusion process utilizing a thermal process carried out during formation of said interlayer insulating film.

3. The semiconductor device manufacturing method according to claim 1, wherein

said first and second extension-forming side walls include side walls further containing a pocket-forming impurity of a second conductivity type, and said step (f) comprises a step of further forming first and second pocket regions adjacent to said first and second main source/drain regions through a second diffusion process where said pocket-forming impurity serves as a diffusion source.

4. The semiconductor device manufacturing method according to claim 3, wherein said pocket-forming impurity has a larger diffusion coefficient than said first extension-forming impurity.

5. The semiconductor device manufacturing method according to claim 3, wherein

said step (f) includes a step of forming an interlayer insulating film all over the surface of said semiconductor substrate including said first transistor, and

said first and second diffusion processes include diffusion processes performed at the same time by utilizing a thermal process carried out during formation of said interlayer insulating film.

6. The semiconductor device manufacturing method according to claim 1, wherein said first real gate electrode is formed using a gate electrode material including a gate electrode material of the first conductivity type.

7. The semiconductor device manufacturing method according to claim 1, further comprising the step of:

(g) performing an impurity introducing process in which an impurity of a second conductivity type is introduced into a predetermined semiconductor region at least including the region in the surface of said semiconductor substrate under the region where said first real gate electrode portion is to be formed.

8. The semiconductor device manufacturing method according to claim 7, wherein

said step (g) includes a step performed after said step (c), and

said impurity introducing process includes an ion implantation process of implanting impurity ions of the second conductivity type through said opening.

9. The semiconductor device manufacturing method according to claim 8, wherein

said ion implantation process in said step (g) includes a process of implanting the ions at an angle of zero degree with respect to a normal of the formation surface of said semiconductor substrate.

10. The semiconductor device manufacturing method according to claim 8, wherein

said ion implantation process in said step (g) further includes a process of implanting the ions at an angle of 5 to 15 degrees with respect to the normal of the formation surface of said semiconductor substrate.

11. The semiconductor device manufacturing method according to claim 1, wherein

said semiconductor substrate includes first and second formation regions,

said temporary gate electrode portion is composed of a stacked structure of a temporary gate insulating film and a temporary gate electrode,

said step (a) includes the steps of:

(a-1) forming said temporary gate electrode portion on said first formation region and forming a second real gate electrode portion having a stacked structure of a second real gate insulating film and a second real gate electrode on said second formation region; and

(a-2) introducing a first source/drain forming impurity of the first conductivity type by using said temporary gate electrode portion as a mask to form said first and second main source/drain regions, and

said step (b) includes a step of further forming third and fourth extension-forming side walls on sides of said second real gate electrode, said third and fourth extension-forming side walls contain a second extension-forming impurity of a second conductivity type,

said manufacturing method further comprising the step of;

(h) after said step (b), introducing a second source/drain forming impurity of the second conductivity type by using said second real gate electrode and said third and fourth extension-forming side walls as masks to form third and fourth main source/drain regions of the second conductivity type in the surface of said second formation region in areas separated by the region under said second real gate electrode and said third and fourth extension-forming side walls, wherein

said step (f) includes a step of further forming third and fourth extension regions of the second conductivity type adjacent respectively to said third and fourth main source/drain regions through a third diffusion process where said second extension-forming impurity in said third and fourth extension-forming side walls serves as a diffusion source, and

said second real gate insulating film, said second real gate electrode, said third and fourth main source/drain regions and said third and fourth extension regions define an insulated-gate, second transistor of the second conductivity type.

12. The semiconductor device manufacturing method according to claim 11, wherein

said first conductivity type includes N type and said second conductivity type includes P type,

said first and second extension-forming side walls are formed by using a material including PSG (Phospho-Silicate Glass) and said first extension-forming impurity includes phosphorus, and

said third and fourth extension-forming side walls are formed by using a material including BSG (Boron-Silicate Glass) and said second extension-forming impurity includes boron.

13. The semiconductor device manufacturing method according to claim 11, wherein

said first conductivity type includes P type and said second conductivity type includes N type,

said first and second extension-forming side walls are formed by using a material including BSG and said first extension-forming impurity includes boron, and

said third and fourth extension-forming side walls are formed by using a material including PSG and said second extension-forming impurity includes phosphorus.

14. The semiconductor device manufacturing, method according to claim 11, further comprising the step of:

(i) before said step (a), separating said first and second formation regions with an element isolation region.

15. The semiconductor device manufacturing method according to claim 11, wherein

said first and second auxiliary side walls include side walls containing said second extension-forming impurity, and

said step (b) includes a step of simultaneously forming said first and second auxiliary side walls and said third and fourth extension-forming side walls.

16. The semiconductor device manufacturing method according to claim 11, wherein

said first real gate electrode is formed by using a gate electrode material including a gate electrode material of the first conductivity type, and

said second real gate electrode is formed by using a gate electrode material including a gate electrode material of the second conductivity type.

17. The semiconductor device manufacturing method according to claim 16, wherein

said temporary gate electrode is formed by using a gate electrode material including a gate electrode material of the second conductivity type, and said step (a-1) includes a step of simultaneously forming said temporary gate electrode and said second real gate electrode.