Method to reduce polysilicon depletion in MOS transistors

• US 6,387,784 B1
• Filed: 03/19/2001
• Issued: 05/14/2002
• Est. Priority Date: 03/19/2001
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Chong, Yung Fu, Chan, Lap, Pey, Kin Leong, Cha, Randall Cher Liang
• Primary Examiner(s): Booth, Richard
• Application Number:
  US09/810,121
• Time in Patent Office: 421 Days
• Field of Search: 438/585-597
• US Class Current: 438/585
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method is provided to reduce poly depletion in MOS transistors. Conventionally, after a polysilicon electrode has been doped, an anneal step is usually performed to activate the dopants. However, the anneal step may be insufficient to drive the implanted impurities down the entire depth of the polysilicon electrode. Consequently, a portion of the polysilicon gate nearest to the gate oxide will be depleted of dopants. This poly depletion will have a detrimental effect on the control of the threshold voltage, and hence on the performance of the device. It is disclosed in the present invention a method of forming polysilicon gates where dopant depletion at the interface near the gate oxide layer is alleviated substantially by using laser annealing; however, by first pre-amorphizing the polycrystalline silicon prior to ion (implantation to a desired depth such that during laser annealing the dopants will diffuse uniformly to a melt depth. In this manner, poly depletion effect is greatly reduced and hence performance of the device improved. The disclosed method is applicable to both n⁺ doped polysilicon gates (NMOS) and p⁺ doped polysilicon gates (PMOS).

Claims

1. A method of forming a polysilicon electrode with reduced dopant depletion comprising:

providing a substrate;

forming a dielectric layer over said substrate;

forming a polysilicon layer over said dielectric layer;

in-situ amorphizing upper portion of said polysilicon layer by implanting ions into said polysilicon layer to form an amorphous (α

-Si) layer over said polysilicon layer;

then

doping said polysilicon layer by implanting ions; and

performing, laser irradiation of selected wavelength and fluence to melt and regrow said α

-Si layer while at the same time driving said ions deeply into said polysilicon layer adjacent said underlying dielectric layer.

2. The method of claim 1, wherein said substrate is silicon.

3. The method of claim 1, wherein said dielectric layer is formed by thermal growth at a temperature between about 700 to 1000°

C.

4. The method of claim 1, wherein said dielectric layer has a thickness between about 100 to 600 Å

.

5. The method of claim 1, wherein said polysilicon layer is formed through an LPCVD method employing silane SiH₄ as a silicon source material at a temperature range between about 400 to 700°

C.

6. The method of claim 1, wherein said polysilicon layer has a thickness between about 1100 to 5000 Å

.

7. The method of claim 1, wherein said in-situ amorphizing said upper portion of said polysilicon layer is accomplished by ion implanting Si at a dosage level between about 1×

10¹⁴ to 1×

10¹⁶ atoms/cm², and energy level between about 50 to 200 KeV.

8. The method of claim 1, wherein said α

-Si layer has a thickness between about 100 to 1500 Å

.

9. The method of claim 1, wherein said doping said polysilicon layer is accomplished by implanting B⁺, BF₂⁺,P⁺, As⁺ ions at a dosage level between about 5×

10¹⁴ to 1×

10¹⁶ atoms/cm², and energy level between about 0.5 to 50 KeV.

10. The method of claim 1, wherein said performing said laser irradiation is accomplished at a wavelength between about 157 to 308 nanometers, and fluence of between about 0.1 to 1.5 J/cm².

11. A method of reducing polysilicon depletion in polysilicon electrodes in MOS transistors comprising the steps of:

providing a substrate;

forming a pad oxide layer over said substrate;

forming a nitride layer over said pad oxide layer;

patterning said nitride layer to form a trench over said pad oxide layer;

removing said pad oxide layer and exposing said substrate at the bottom of said trench;

optionally forming and removing a sacrificial layer;

forming a gate oxide layer over said substrate at the bottom of said trench;

forming a polysilicon layer over said substrate, including within said trench;

performing chemical mechanical polishing (CMP) to remove excess polysilicon over said trench;

selective etching said polysilicon layer in said trench to a desired thickness;

in-situ amorphizing upper portion of said polysilicon layer by implanting ions into said polysilicon layer to form an amorphous (α

-Si) layer over said polysilicon layer;

doping said polysilicon layer by implanting ions;

performing laser irradiation of selected wavelength and fluence to melt and regrow said α

-Si layer while at the same time driving said ions deeply into said polysilicon electrode reaching but adjacent said underlying oxide layer; and

continuing the completion of said MOS transistor by a depositing another material into said trench followed by CMP to form a contact.

12. The method of claim 11, wherein said substrate is silicon.

13. The method of claim 11, wherein said pad oxide layer is formed. by thermal growth at a temperature between about 700 to 1000°

C.

14. The method of claim 11, wherein said pad oxide layer has a thickness between about 100 to 600 Å

.

15. The method of claim 11, wherein said nitride layer is formed by reacting dichlorosilane (SiCl₂H₂), or silane (SiH₄), with ammonia (NH₃) in an CVD at a temperature between about 300 to 900°

C.

16. The method of claim 11, wherein said nitride layer has a thickness between about 1000 to 3000 Å

.

17. The method of claim 11, wherein said gate oxide layer is thermally grown at a temperature between about 900 to 1200°

C., or deposited using CVD.

18. The method of claim 11, wherein said gate oxide has a thickness between about 10 to 150 Å

.

19. The method of claim 11, wherein said polysilicon layer is formed through an LPCVD method employing silane SiH₄ as a silicon source material at a temperature range between about 400 to 700°

C.

20. The method of claim 11 wherein said polysilicon layer has a thickness between about 1100 to 5000 Å

.

21. The method of claim 11, wherein said etching said polysilicon layer is accomplished with a recipe comprising Cl₂, HeO₂,HBr, He.

22. The method of claim 11, wherein said in-situ amorphizing said upper portion of said polysilicon layer is accomplished by ion implanting Si or Ge⁺ at a dosage level between about 1×

10¹⁴ to 1×

10¹⁶ atoms/cm², and energy level between about 50 to 200 KeV.

23. The method of claim 11, wherein said α

-Si layer has a thickness between about 100 to 1500 Å

.

24. The method of claim 11, wherein said doping said polysilicon layer is accomplished by implanting B⁺, BF₂⁺,P⁺, As⁺ ions at a dosage level between about 5×

10⁴ to 1×

10¹⁶ atoms/cm², and energy level between about 0.5 to 50 KeV.

25. The method of claim 11, wherein said performing said laser irradiation is accomplished at a wavelength between about 157 to 308 nanometers, and fluence of between about 0.1 to 1.5 J/cm².