Method of forming barrier and seed layers for electrochemical deposition of copper

• US 6,387,800 B1
• Filed: 12/20/1999
• Issued: 05/14/2002
• Est. Priority Date: 12/20/1999
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chung-Shi, Shue, Shau-Lin
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/467,117
• Time in Patent Office: 876 Days
• Field of Search: 438/723, 438/740, 438/743, 438/785, 438/653-655, 438/680-688, 257/751-754, 257/762, 204/192, 216/67, 216/76
• US Class Current: 438/653
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A process in the fabrication of integrated circuits has been developed for copper diffusion barrier layer and copper seed layer. The invention teaches a method of combining ion metal plasma (IMP) deposition techniques, i.e., with and without AC/Rf bias, in a series of steps or cycles (of at least four or more cycles depending on device geometry), of AC/Rf bias “ON”, AC/Rf bias “OFF”, to form both the copper metal diffusion barrier (reactive IMP) and then subsequently, the copper seed layer. The current invention applies to lining both a single and dual damascene structure to form a copper metal barrier layer, TaN, and copper seed layer for interconnects and vias prior to electrochemical deposition (ECD) of copper.

Claims

1. A method for fabricating integrated circuits on a substrate with single or dual damascene structure, the method comprising:

providing a substrate or substrate module having a layer of dielectric, interlevel dielectric (ILD), or an interconnect line or conducting region;

providing a first level of conducting wiring being defined and embedded in a first layer of insulator;

depositing a second layer of insulator on the first layer of insulator;

patterning and etching the second layer of insulator to form both single and dual damascene trench/via and interconnect structures;

depositing on the second layer of insulator by reactive ion metal plasma (IMP) a TaN barrier layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias On, AC/Rf bias OFF steps and patterning barrier layer;

depositing on the barrier layer by ion metal plasma (IMP) a copper seed layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning said seed layer;

depositing on the copper seed layer by electrochemical deposition (ECD) a copper conducting material by plating copper in a sulfuric acid solution with a solution or plating bath temperature from approximately −

40 to 40°

C., at a deposition rate of approximately 1,000 Angstroms per minute, forming a copper conducting material thickness from approximately 5,000 to 20,000 Angstroms thick, forming copper grains or crystals from approximately 1,000 to 20,000 Angstroms in size, having a preferred (111) crystal orientation, with a re-crystallization temperature of approximately 100 to 300°

C.;

polishing back by chemical mechanical polishing (CMP) the excess copper conducting material, seed layer, and barrier layer.

2. The method of claim 1, wherein said substrate is semiconductor single crystal silicon or an IC module.

3. The method of claim 1, wherein said substrate is semiconductor single crystal silicon, N-type or P-type, with conducting regions being:

doped source and drain regions of MOSFET and CMOS devices, comprised of interconnect wiring and contact vias selected from the group consisting of Cu, AlCu, W, with silicide, polysilicon gate structures of MOSFET and CMOS devices.

4. The method of claim 1, wherein first and second layers of insulators or dielectric layers form intermetal dielectric layers (IMD) that are comprised or composed of silicon dioxide or silicon oxide.

5. The method of claim 1, wherein in the trench or channel and said via hole contact is lined with a diffusion barrier liner, which also aids adhesion, deposited by a special reactive ion metal plasma (IMP) which is a sputtering physical vapor deposition (PVD) technique, the liner material comprised of TaN, thickness from 100 to 500 Angstroms, extending to Ta/TaN/TaN barrier layers for better adhesion.

6. The method of claim 1, wherein the trench or channel and said via hole contact is lined with TaN, a diffusion barrier liner, deposited by a special reactive ion metal plasma (IMP) technique, wherein the power is cycled with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps.

7. The method of claim 1, wherein the barrier layer process details are as follows:

reactive ion metal plasma (IMP) sputter, a cluster tool, sputter target size 300 mm, gases Ar and N₂, Ar flow rate of about 50 sccm, substrate temperature of about 100°

C., total film thickness deposited of about 300 Angstroms, deposition rate of about 600 Angstroms per minute, number of cycles from about 4 to 10, thickness deposition per step is equal to (total film thickness/number of steps), order or sequence of steps is AC “

OFF”

to AC “

ON”

, to AC “

OFF”

to AC “

ON”

, etc., pressure of 20 mTorr, DC magnetron power of 1 KW, AC/Rf power of 1.5 KW, AC bias of 350 W, Rf frequency of about 2 MHz.

8. The method of claim 1, wherein in the trench or channel and said via hole contact is lined with a copper seed layer deposited by special ion metal plasma (IMP) which is a sputtering physical vapor deposition (PVD) technique, the seed layer type material is comprised of a copper layer, thickness from 800 to 2500 Angstroms.

9. The method of claim 1, wherein the trench or channel and said via hole contact is lined with a copper seed layer deposited by a special ion metal plasma (IMP) technique, wherein the power is cycled with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps.

10. The method of claim 1, wherein the seed layer process details are as follows:

ion metal plasma (IMP) sputter, a cluster tool, sputter target size 300 mm, Ar gas, Ar flow rate of about 50 sccm, substrate temperature of about 25°

C., total film thickness deposited from about 800 to 2500 Angstroms, deposition rate of about 1500 Angstroms per minute, number of cycles from about 4 to 10, thickness deposition per step is equal to (total film thickness/number of steps), order or sequence of steps is AC “

OFF”

to AC “

ON”

, to AC “

OFF”

to AC “

ON”

, etc., pressure of 40 mTorr, DC magnetron power of 1 KW, DC bias of 350 V, AC/Rf power of 3 KW, AC bias of 350 W, Rf frequency of about 2 MHz.

11. The method of claim 1, wherein the conducting material layers for conducting interconnect lines and said via contacts comprise the following conducting type materials:

electrochemical deposition (ECD) of copper, upon the copper seed layer, ECD Cu thickness from 5000 to 20000 Angstroms.

12. The method of claim 1, wherein the ECD copper is electrochemically deposited in the trench/via structures without seams or voids upon said seed layer and said barrier layer.

13. The method of claim 1, wherein multilevel conducting structures are fabricating by repeating the process described herein.

14. The method of claim 1, wherein each level of conducting structure is planarized by removing excess conducting material, including planarization by chemical mechanical polish (CMP), milling, ion milling, and/or etching.

15. A method for fabricating integrated circuits on a substrate with single or dual damascene structure, the method comprising:

providing a semiconductor substrate or substrate module having a layer of dielectric silicon oxide, interlevel dielectric (ILD), or a copper interconnect line or conducting P-N junction region;

providing a first level of copper conducting wiring being defined and embedded in a first layer of silicon oxide insulator;

depositing a second layer of silicon oxide insulator on the first layer of insulator;

patterning and etching the second layer of insulator to form both single and dual damascene trench/via and interconnect structures;

deposition on the second layer of insulator by reactive ion metal plasma (IMP) a TaN barrier layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning barrier layer;

depositing on the barrier layer by ion metal plasma (IMP) a copper seed layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning said seed layer;

depositing on the copper seed layer by electrochemical deposition (ECD) a copper conducting material by plating copper in a sulfuric acid solution with a solution or plating bath temperature from approximately −

40 to 40°

C., at a deposition rate of approximately 1,000 Angstroms per minute, forming a copper conducting material thickness from approximately 5,000 to 20,000 Angstroms thick, forming copper grains or crystals from approximately 1,000 to 20,000 Angstroms in size, having a preferred (111) crystal orientation, with a re-crystallization temperature of approximately 100 to 300°

C.;

polishing back by chemical mechanical polishing (CMP) the excess copper conducting material, seed layer, and barrier layer.

16. The method of claim 15, wherein multilevel conducting structures are fabricating by repeating the process described herein.

17. The method of claim 15, wherein said substrate is semiconductor single crystal silicon or an IC module.

18. The method of claim 15, wherein said substrate is semiconductor single crystal silicon, N-type or P-type, with conducting regions being:

doped source and drain regions of MOSFET and CMOS devices, comprised of interconnect wiring and contact vias selected from the group consisting of Cu, AlCu, W, with silicide, polysilicon gate structures of MOSFET and CMOS devices.

19. The method of claim 15, wherein first and second layers of insulators or dielectric layers form intermetal dielectric layers (IMD) that are comprised or composed of silicon dioxide or silicon oxide.

20. The method of claim 15, wherein in the trench or channel and said via hole contact is lined with a diffusion barrier liner, which also aids adhesion, deposited by a special reactive ion metal plasma (IMP) which is a sputtering physical vapor deposition (PVD) technique, the liner material comprised of TaN, thickness from 100 to 500 Angstroms, extending to Ta/TaN/TaN barrier layers for better adhesion.

21. The method of claim 15, wherein the trench or channel and said via hole contact is lined with TaN, a diffusion barrier liner, deposited by a special reactive ion metal plasma (IMP) technique, wherein the power is cycled with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps.

22. The method of claim 15, wherein the barrier layer process details are as follows:

reactive ion metal plasma (IMP) sputter, a cluster tool, sputter target size 300 mm, gases Ar and N₂, Ar flow rate of about 50 sccm, substrate temperature of about 100°

C., total film thickness deposited of about 300 Angstroms, deposition rate of about 600 Angstroms per minutes, number of cycles from about 4 to 10, thickness deposition per step is equal to (total film thickness/number of steps), order or sequence of steps is AC “

OFF”

to AC“

ON”

, to AC “

OFF”

to AC “

ON”

, etc., pressure of 20 mTorr, DC magnetron power of 1 KW, AC/Rf power of 1.5 KW, AC bias of 350 W, Rf frequency of about 2 MHz.

23. The method of claim 15, wherein in the trench or channel and said via hole contact is lined with a copper seed layer deposited by special ion metal plasma (IMP) which is a sputtering physical vapor deposition (PVD) technique, the seed layer type material is comprised of a copper layer, thickness from 800 to 2500 Angstroms.

24. The method of claim 15, wherein the trench or channel and said via hole contact is lined with a copper seed layer deposited by a special ion metal plasma (IMP) technique, wherein the power is cycled with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps.

25. The method of claim 15, wherein the seed layer process details are as follows:

ion metal plasma (IMP) sputter, a cluster tool, sputter target size 300 mm, Ar gas, Ar flow rate of about 50 sccm, substrate temperature of about 25°

C., total film thickness deposited from about 800 to 2500 Angstroms, deposition rate of about 1500 Angstroms per minute, number of cycles from about 4 to 10, thickness deposition per step is equal to (total film thickness/number of steps), order or sequence of steps is AC “

OFF”

to AC “

ON”

, to AC “

OFF”

to AC “

ON”

, etc., pressure of 40 mTorr, DC magnetron power of 1 KW, DC bias of 350 V, AC/Rf power of 3 KW, AC bias of 350 W, Rf frequency of about 2 MHz.

26. The method of claim 15, wherein the conducting material layers for conducting interconnect lines and said via contacts comprise the following conducting type materials:

electrochemical deposition (ECD) of copper, upon the copper seed layer, ECD Cu thickness from 5000 to 20000 Angstroms.

27. The method of claim 15, wherein the ECD copper is electrochemically deposited in the trench/via structures without seams or voids upon said seed layer and said barrier layer.

28. The method of claim 15, wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP), milling, ion milling, and/or etching.

29. A method for fabricating MOSFET and CMOS devices on a silicon semiconductor substrate with single or dual damascene structures using electrochemical deposition (ECD) of copper and ion metal plasma (IMP) deposition of copper seed layer and barrier layer, the method comprising:

providing a semiconductor substrate or substrate module having a layer of dielectric silicon oxide, interlevel dielectric (ILD), or a copper interconnect line or conducting P-N junction region;

providing a first level of copper conducting wiring being defined and embedded in a first layer of silicon oxide insulator;

depositing a second layer of silicon oxide insulator on the first layer of insulator;

patterning and etching the second layer of insulator to form both single and dual damascene trench/via and interconnect structures;

depositing on the second layer of insulator by reactive ion metal plasma (IMP) a TaN barrier layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning barrier layer;

depositing on the barrier layer by ion metal plasma (IMP) a copper seed layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning said seed layer;

depositing on the copper seed layer by electrochemical deposition (ECD) a copper conducting material by plating copper in a sulfuric acid solution with a solution or plating bath temperature from approximately −

40 to 40°

C., at a deposition rate of approximately 1,000 Angstroms per minute, forming a copper conducting material thickness from approximately 5,000 to 20,000 Angstroms thick, forming copper grains or crystals from approximately 1,000 to 20,000 Angstroms in size, having a preferred (111) crystal orientation, with a re-crystallization temperature of approximately 100 to 300°

C.;

polishing back by chemical mechanical polishing (CMP) the excess copper conducting material, seed layer, and barrier layer.

30. The method of claim 29, wherein multilevel conducting structures are fabricating by repeating the process described herein.

31. The method of claim 29, wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP), milling, ion milling, and/or etching.

32. The method of claim 29, wherein said substrate is semiconductor single crystal silicon or an IC module.

33. The method of claim 29, wherein said substrate is semiconductor single crystal silicon, N-type or P-type, with conducting regions being:

doped source and drain regions of MOSFET and CMOS devices, comprised of interconnect wiring and contact vias selected from the group consisting of Cu, AlCu, W, with silicide, polysilicon gate structures of MOSFET and CMOS devices.

34. The method of claim 29, wherein first and second layers of insulators or dielectric layers form intermetal dielectric layers (IMD) that are comprised or composed of silicon dioxide or silicon oxide.

35. The method of claim 29, wherein in the trench or channel and said via hole contact is lined with a diffusion barrier liner, which also aids adhesion, deposited by a special reactive ion metal plasma (IMP) which is a sputtering physical vapor deposition (PVD) technique, the liner material comprised of TaN, thickness from 100 to 500 Angstroms, extending to Ta/TaN/TaN barrier layers for better adhesion.

36. The method of claim 29, wherein the trench or channel and said via hole contact is lined with TaN, a diffusion barrier liner, deposited by a special reactive ion metal plasma (IMP) technique, wherein the power is cycled with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps.

37. The method of claim 29, wherein the barrier layer process details are as follows:

reactive ion metal plasma (IMP) sputter, a cluster tool, sputter target size 300 mm, gases Ar and N₂, Ar flow rate of about 50 sccm, substrate temperature of about 100°

C., total film thickness deposited of about 300 Angstroms, deposition rate of about 600 Angstroms per minute, number of cycles from about 4 to 10, thickness deposition per step is equal to (total film thickness/number of steps), order or sequence of steps is AC “

OFF”

to AC “

ON”

, to AC “

OFF”

to AC “

ON”

, etc., pressure of 20 mTorr, DC magnetron power of 1 KW, AC/Rf power of 1.5 KW, AC bias of 350 W, Rf frequency of about 2 MHz.

38. The method of claim 29, wherein in the trench or channel and said via hole contact is lined with a copper seed layer deposited by special ion metal plasma (IMP) which is a sputtering physical vapor deposition (PVD) technique, the seed layer type material is comprised of a copper layer, thickness from 800 to 2500 Angstroms.

39. The method of claim 29, wherein the trench or channel and said via hole contact is lined with a copper seed layer deposited by a special ion metal plasma (IMP) technique, wherein the power is cycled with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps.

40. The method of claim 29, wherein the seed layer process details are as follows:

ion metal plasma (IMP) sputter, a cluster tool, sputter target size 300 mm, Ar gas, Ar flow rate of about 50 sccm, substrate temperature of about 25°

C., total film thickness deposited from about 800 to 2500 Angstroms, deposition rate of about 1500 Angstroms per minute, number of cycles from about 4 to 10, thickness deposition per step is equal to (total film thickness/number of steps), order or sequence of steps is AC “

OFF”

to AC “

ON”

, to AC “

OFF”

to AC “

ON”

, etc., pressure of 40 mTorr, DC magnetron power of 1 KW, DC bias of 350 V, AC/Rf power of 3 KW, AC bias of 350 W, Rf frequency of about 2 MHz.

41. The method of claim 29, wherein the conducting material layers for conducting interconnect lines and said via contacts comprise the following conducting type materials:

electrochemical deposition (ECD) of copper, upon the copper seed layer, ECD Cu thickness from 5000 to 20000 Angstroms.

42. The method of claim 29, wherein the ECD copper is electrochemically deposited in the trench/via structures without seams or voids upon said seed layer and said barrier layer.