Power semiconductor devices having trench-based gate electrodes and field plates

• US 6,388,286 B1
• Filed: 08/18/1999
• Issued: 05/14/2002
• Est. Priority Date: 10/26/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US09/377,006
• Time in Patent Office: 1,000 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/333, 257/334, 257/339, 257/488, 257/471, 257/476
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (C_GD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation. Methods according to the present invention also include the steps of forming a trench in a semiconductor substrate and then forming an insulated source electrode in and adjacent a bottom of the trench by forming a first electrically insulating layer on a bottom and sidewall of the trench, then forming a first electrically conductive layer on the first electrically insulating layer and then forming a second electrically insulating layer on the first electrically conductive layer using a thermal oxidation technique, for example. An insulated gate electrode is then formed in and adjacent a top of trench. Steps are also provided to form a source region of first conductivity type in the semiconductor substrate and form a second source electrode electrically connected to the source region and the insulated source electrode.

Claims

1. A semiconductor switching device, comprising:

a semiconductor substrate having first and second opposing faces;

a drift region of first conductivity type in said substrate;

first and second trenches that extend in the first face of said substrate and define an inactive transition region mesa therebetween into which said drift region extends;

a vertical MOSFET in an active region within said substrate, said vertical MOSFET comprising an insulated gate electrode in said second trench, and a source region of first conductivity type and a base region of second conductivity type that extend adjacent a sidewall of said second trench, said base region forming a P-N rectifying junction with said drift region at a first depth relative to the first face;

a breakdown shielding region of second conductivity type that extends in the transition region mesa and adjacent the first face and defines a P-N rectifying junction with said drift region;

a field plate insulating region lining a sidewall and bottom of said first trench; and

a field plate extending in said first trench and on said field plate insulating region;

wherein said breakdown shielding region has a maximum depth relative to the first face that is greater than the first depth and is less than a depth of said first and second trenches; and

wherein said breakdown shielding region also has a sufficient second conductivity type doping concentration therein that in combination with the maximum depth causes avalanche breakdown to occur in the inactive transition region mesa before it occurs at the P-N junction within the active region, when the device is biased into reverse breakdown.

2. A semiconductor switching device, comprising:

a semiconductor substrate having first and second opposing faces;

a drain region of first conductivity type in said substrate, adjacent the second face;

a drift region of first conductivity type in said substrate, said drift region forming a nonrectifying junction with said drain region and having a graded first conductivity type doping concentration therein which decreases in a direction from said drain region towards the first face;

a first trench in said substrate at the first face, said first trench having first and second opposing sidewalls which extend from the first face into said drift region;

a second trench in said substrate at the first face, said second trench having first and second opposing sidewalls which extend from the first face into said drift region, said second sidewall of said first trench and said second sidewall of said second trench defining a transition region mesa therebetween into which said drift region extends;

a source region of first conductivity type in said substrate, said source region extending opposite the first sidewall of said first trench and adjacent the first face;

a base region of second conductivity type in said substrate, said base region extending between said source region and said drift region and forming a first P-N junction with said source region and a second P-N junction with said drift region;

a breakdown shielding region of second conductivity type that extends in the transition region mesa and is electrically connected to said source region, said breakdown shielding region having a maximum depth relative to the first face that is greater than a depth of the second P-N junction and is less than a depth of said first and second trenches and also having a sufficient second conductivity type doping concentration therein that in combination with the maximum depth causes avalanche breakdown to occur in the transition region mesa before it occurs at the second P-N junction when the device is sufficiently reverse-biased;

a gate insulating region of nonuniform thickness lining the first and second sidewalls and a bottom of said first trench;

a first field plate insulating region lining the first and second sidewalls and a bottom of said second trench;

a gate electrode in said first trench, on said gate insulating region; and

a field plate in said second trench, on said first field plate insulating region.

3. The device of claim 2, wherein the first sidewall of said first trench defines a first interface between said base region and said gate insulating region and a second interface between said drift region and said gate insulating region;

and wherein said gate insulating region has a first thickness as measured between said gate electrode and said first interface and a second thickness, greater than the first thickness, as measured between said gate electrode and said second interface.

4. The device of claim 3, wherein the first thickness is less than about 750 Å

; and

wherein said second thickness is greater than about 1500 Å

.

5. The device of claim 3, wherein said first field plate insulating region has a uniform thickness.

6. The device of claim 5, further comprising:

a second field plate insulating region on the first face; and

a field plate extension on the second field plate insulating region, opposite the first face.

7. The device of claim 6, wherein said field plate extension and said field plate are electrically connected together and are electrically connected to said gate electrode or said source region.

8. The device of claim 7, wherein the transition region mesa is devoid of a source region of first conductivity type therein.

9. The device of claim 8, further comprising a source electrode on the first face, ohmically contacting said breakdown shielding region and said source region.

10. The device of claim 9, wherein said breakdown shielding region is more highly doped than said base region.

11. The device of claim 10, wherein the bottom of said first trench defines an interface between said drain region and said gate insulating region.