Power semiconductor array on a DCB substrate

• US 6,388,344 B1
• Filed: 12/20/1999
• Issued: 05/14/2002
• Est. Priority Date: 06/18/1997
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Klotz, Frank, Lorenz, Leo
• Primary Examiner(s): Ballato, Josie
• Assistant Examiner(s): POLK, SHARON A
• Application Number:
  US09/467,350
• Time in Patent Office: 876 Days
• Field of Search: 307/85, 307/109, 307/115, 307/113, 257/753, 257/783, 257/784, 257/207, 257/500, 257/502, 257/723, 257/724, 257/762, 257/691
• US Class Current: 307/113
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/12 Arrangements for reducing harmonics from ac input or output
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

A power semiconductor array on a direct copper bonding (DCB) semiconductor substrate is created, in which the interference emissions propagated via its terminal lines are eliminated, or at least greatly reduced, directly on the semiconductor device. The power semiconductor array on the DCB substrate includes a first intermediate circuit terminal connected to a positive potential, a second intermediate circuit terminal connected to a negative potential, and at least one load terminal. The power semiconductor array further includes at least two power switches for connecting the load terminal to the first and second intermediate circuit terminals in alternation. The power semiconductor array is characterized by bridging connections that connect at least some of the terminals of the power semiconductor array that lead to the outside to one another in pairs, so that interference circuits within the power semiconductor array are closed.

Claims

1. A power semiconductor array, comprising:

terminals including a first intermediate circuit terminal to be connected to a positive potential, a second intermediate circuit terminal to be connected to a negative potential, at least one load terminal, and a ground terminal;

at least two power switches, including a first power switch and a second power switch, connecting said at least one load terminal to said first and second intermediate circuit terminals in alternation; and

a direct copper bonding substrate having said at least two power transistors disposed thereon, said direct copper bonding substrate including an insulation layer having a first insulation layer, a second insulation layer, and a conductive intermediate layer disposed between said first insulation layer and said second insulation layer, said conductive intermediate layer connected to one of said first and second intermediate circuit terminals to capacitively connect one of said first and second intermediate circuit terminals to said at least two power switches.

2. The power semiconductor array according to claim 1,

including a first connecting line disposed between said first intermediate circuit terminal and said first power switch, and

a second connecting line disposed between said second intermediate circuit terminal and said second power switch,

said first connecting line and said second connecting line disposed such that said first and second intermediate circuit terminals are capacitively connected to one another.

3. The power semiconductor array according to claim 1,

wherein said conductive intermediate layer is formed of a material selected from the group consisting of copper and copper alloy.

4. The power semiconductor array according to claim 1,

including a driver stage for triggering said at least two power switches, said driver stage having two driver supply terminals connected at least one of capacitively and

galvanically with at least one of said first and second intermediate circuit terminals.

5. The power semiconductor array according to claim 4,

wherein said two driver supply terminals of said driver stage are inductively coupled to one another.

6. The power semiconductor array according to claim 1,

wherein said at least two power switches include insulated gate bipolar transistors (IGBTs).

7. The power semiconductor array according to claim 1,

wherein said at least two power switches include metal-oxide-semiconductor field-effect transistors (MOSFETs).

8. The power semiconductor array according to claim 6,

wherein said at least two power switches define a switching path, and including reverse diodes disposed parallel to said switching path.

9. The power semiconductor array according to claim 7,

wherein said at least two power switches define a switching path, and including reverse diodes disposed parallel to said switching path.

10. The power semiconductor array according to claim 1,

wherein said at least two power switches each include a plurality of operatively series-connected power switch elements.

11. The power semiconductor array according to claim 1,

wherein said at least two power switches each include a plurality of operatively parallel-connected power switch elements.