Schmitt trigger with hysteresis and previous-state memory

• US 6,388,488 B1
• Filed: 11/02/2000
• Issued: 05/14/2002
• Est. Priority Date: 11/02/2000
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Ho, Franklin Sai-Wai
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/704,870
• Time in Patent Office: 558 Days
• Field of Search: 327/108, 327/109, 327/111, 327/112, 327/170, 327/206, 327/205, 327/389, 326/26, 326/27, 326/28, 326/57
• US Class Current: 327/206
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

Described is a level-detection circuit having hysteresis and which may be powered down without losing the last state of the circuit. The level-detection circuit includes a first detection circuit, a trip-level adjustment circuit, and a second detection circuit. The first detection circuit may be essentially an inverter, with the output signal of the inverter fed to an input of the second detection circuit. The trip-level adjustment circuit is connected to the output signal and has control connections tied to the input signal. The trip-level adjustment circuit also includes control connections tied to the output signal of the circuit. In short, the trip-level adjustment circuit is configured such that one element of the trip-level adjustment circuit is connected in parallel with one element of the inverter of the first detection circuit when the input signal moves from a one potential to another potential. In addition, the trip-level adjustment circuit may include another element connected in parallel with another element of the inverter of the first detection circuit when the input signal moves in the opposite direction, e.g. from the other potential to the one potential. Moreover, the circuit includes latching circuitry, under control of an enable signal, configured to latch a last state of the trip-level adjustment circuit during a power-down event so that the input signal to the second detection circuit will have the same state when the circuit is powered back up.

Claims

1. An apparatus for generating an output signal based on an input signal, comprising:

a first detection circuit configured to detect a potential of the input signal and that provides an intermediate output signal having a level based on the potential of the input signal, the first detection circuit having an unaltered threshold potential at which the first detection circuit changes a state of the intermediate output signal, the first detection circuit being coupled to receive an enable signal, the first detection circuit being further configured to be deactivated in response to the enable signal being deasserted;

a second detection circuit coupled to the intermediate output signal and being configured to change a state of the output signal in response to the level of the intermediate output signal changing state; and

a trip-level adjustment circuit coupled to the first detection circuit and configured to influence the first detection circuit such that the intermediate output signal changes state when the input signal is at some potential different from the unaltered threshold potential, the trip-level adjustment circuit comprising a first subcircuit having a first control mechanism coupled to the output signal of the second detection circuit and a first influence control mechanism under control of the input signal;

wherein the first control mechanism is sized sufficiently large in comparison to the first influence control mechanism such that a voltage drop across the first control mechanism is much less than a voltage drop across the first influence control mechanism.

2. The apparatus of claim 1 wherein the first detection circuit comprises a first subcircuit and a second subcircuit configured as an inverter.

3. The apparatus of claim 2 wherein the first subcircuit includes a pair of transistors in series and the second subcircuit includes another pair of transistors in series.

4. The apparatus of claim 1 wherein the first subcircuit is coupled to receive a reference potential and to receive the intermediate output signal, the first control mechanism being coupled to the output signal of the second detection circuit such that when the output signal is in a first state the first subcircuit is active and when the output signal is in a second state the first subcircuit is deactivated, the first subcircuit being operative to provide feedback, when activated, to the first detection circuit as the input signal changes from a first potential to a second potential.

5. The apparatus of claim 4 wherein the first subcircuit further comprises a second control mechanism coupled to the input signal, the feedback of the first subcircuit being under control of the second control mechanism.

6. The apparatus of claim 5 wherein the first control mechanism comprises a transistor and the second control mechanism comprises another transistor.

7. The apparatus of claim 4 wherein the trip-level adjustment circuit comprises a second subcircuit coupled to another reference potential and to the intermediate output signal, the second subcircuit including a second control mechanism coupled to the output signal of the second detection circuit such that when the output signal is in the first state the second subcircuit is inactive and when the output signal is in the second state the second subcircuit is active, the second subcircuit being operative to provide feedback, when activated, to the first detection circuit as the input signal changes from the second potential to the first potential.

8. The apparatus of claim 7 wherein the first influence control mechanism is connected between the first control mechanism and the intermediate output signal, and further wherein the second subcircuit further includes a second influence control mechanism under control of the input signal, the second influence control mechanism being connected between the second control mechanism and the intermediate output signal.

9. The apparatus of claim 8 wherein the second control mechanism is sized sufficiently large in comparison to the second influence control mechanism such that a voltage drop across the second control mechanism is much less than a voltage drop across the second influence control mechanism.

21. The apparatus of claim 8, wherein the reference potential of the first subcircuit comprises a supply voltage and the other reference potential of the second subcircuit comprises a circuit ground.

10. An apparatus for generating an output signal based on an input signal, comprising:

a first detection circuit, coupled to receive the input signal, that detects a potential of the input signal and that provides an intermediate output signal having a level based on the potential of the input signal, the first detection circuit having an unaltered threshold potential at which the first detection circuit changes a state of the intermediate output signal, the first detection circuit being coupled to receive an enable signal, the first detection circuit being further configured to be deactivated in response to the enable signal being deasserted;

a second detection circuit coupled to receive the intermediate output signal and being configured to change a state of the output signal in response to the level of the intermediate output signal passing through a second threshold potential;

a trip-level adjustment circuit configured to influence the first detection circuit such that the intermediate output signal passes through the second threshold potential while the input signal is at some potential different from the unaltered threshold potential of the first detection circuit; and

a latching circuit coupled to receive the intermediate output signal and to receive the enable signal, the latching circuit being configured to latch a state of the intermediate output signal in response to the enable signal being deasserted.

11. The apparatus of claim 10 wherein the trip-level adjustment circuit comprises a first subcircuit coupled to receive a reference potential signal and to receive the intermediate output signal, the first subcircuit including a first control mechanism coupled to receive the output signal of the second detection circuit such that when the output signal is in a first state the first subcircuit is activated and when the output signal is in a second state the first subcircuit is deactivated, the first subcircuit further comprising a second control mechanism coupled to receive the input signal and configured to provide feedback to the first detection circuit, when the first subcircuit is activated, as the level of the intermediate output signal changes from a first potential to a second potential.

12. The apparatus of claim 11 wherein the first control mechanism comprises a transistor and the second control mechanism comprises another transistor.

13. The apparatus of claim 11 wherein the trip-level adjustment circuit comprises a second subcircuit coupled to receive another reference potential and to receive the intermediate output signal, the second subcircuit including a third control mechanism coupled to receive the output signal of the second detection circuit such that when the output signal is in the first state the second subcircuit is deactivated and when the output signal is in the second state the second subcircuit is activated, the second subcircuit further comprising a fourth control mechanism coupled to the input signal and configured to provide feedback to the first detection circuit, when the second component is activated, as the intermediate output signal changes from the second potential to the first potential.

14. The apparatus of claim 13 wherein the latching circuit comprises:

a first latching element under control of the enable signal, coupled to the first subcircuit, and being configured to latch a state of the first subcircuit in response to the enable signal being deasserted; and

a second latching element under control of the enable signal, coupled to the second subcircuit, and being configured to latch a state of the second subcircuit in response to the enable signal being deasserted.

15. The apparatus of claim 14 wherein the first latching element comprises a transistor, and the second latching element comprises another transistor.

16. The apparatus of claim 14 wherein the latching circuit further comprises a first latching circuit switch coupled to the first detection circuit and under control of the enable signal, wherein the first latching switch deactivates at least a portion of the first detection circuit in response to the enable signal being deasserted.

17. The apparatus of claim 16 wherein the latching circuit further comprises a second latching circuit switch coupled to the first detection circuit and under control of the enable signal, wherein the first latching switch deactivates at least another portion of the first detection circuit in response to the enable signal being deasserted.

18. The apparatus of claim 17 wherein the first detection circuit comprises a first detection transistor connected in series with a second detection transistor, and wherein the first latching circuit switch is coupled to the first detection transistor such that the first latching circuit switch deactivates the first detection transistor when the enable signal is deasserted, and wherein the second latching circuit switch is coupled to the second detection transistor such that the second latching circuit switch deactivates the second detection transistor when the enable signal is deasserted.

19. The apparatus of claim 18 wherein the first latching circuit switch comprises a transistor, and the second latching circuit switch comprises another transistor.

20. A method for powering down a circuit that generates an output signal based on an input signal, comprising:

receiving an input signal at a level-detection circuit;

generating an intermediate output signal by the level-detection circuit based on the input signal;

receiving the input signal at a trip-level adjustment circuit;

influencing the level-detection circuit by the trip-level adjustment circuit such that a level of the intermediate output signal reaches a trip-level of an output inverter when the input signal is at a potential different from an unaltered threshold potential of the level-detection circuit, the influence being based upon a component in the trip-level adjustment circuit in combination with a component in the level-detection circuit;

receiving an enable signal indicating a power-down event, the intermediate output signal having a last state at the occurrence of the power-down event; and

latching the last state of the intermediate output signal such that when a power-up event occurs, the intermediate output signal is at the last state.