System and method for programming oscillators

• US 6,388,532 B1
• Filed: 02/15/2000
• Issued: 05/14/2002
• Est. Priority Date: 02/15/2000
• Status: Expired due to Fees

• Current Assignee: Cardinal Components, Inc.
• Original Assignee: Cardinal Components, Inc.
• Inventors: Babcock, David J.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/504,176
• Time in Patent Office: 819 Days
• Field of Search: 331/16, 331/18, 331/25, 331/34, 331/44, 331/66, 331/69, 331/116.R, 331/116.FE, 331/158, 331/175, 327/156-159, 375/376, 455/260
• US Class Current: 331/44
• CPC Class Codes: H03L 1/025 and a memory for digitally storing correction values
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A system and method for programming a digitally tunable oscillator is provided. A desired output frequency is received. A tuning effect of a set of digital tuning words on a crystal resonant frequency is determined, and valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on the determined tuning effect are calculated. Valid parameters are preferably calculated based on an intermediate tuning value, sorted by ascending divide parameter of the algorithm, and then evaluated in sorted order for ability of a tuning effect to null frequency error to within the error tolerance. The valid set of calculated parameters are then programmed into a nonvolatile memory. The oscillator control parameters may remain unprogrammed until all necessary parameters are defined. Because the device may be programmed in a single step, without intermediate presumption of nominal crystal frequency, the final plate process may be unnecessary. A high accuracy may be obtained by searching through the complete set of available parameters for a set that meets a frequency and tolerance specification. The oscillator is preferably a Cypress CY2037 device.

Claims

1. A method for programming a digitally tunable oscillator, comprising the steps of:

(a) receiving a desired output frequency;

(b) determining a tuning effect of a set of digital tuning words on a crystal resonant frequency;

(c) calculating valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on the determined tuning effect; and

(d) programming in a nonvolatile memory a valid set of calculated parameters.

2. The method according to claim 1, further comprising the steps of inputting a desired maximum error tolerance.

3. The method according to claim 1, wherein the algorithm comprises a phase lock loop frequency synthesis having a multiply parameter and a divide parameter for frequency translation.

4. The method according to claim 1, wherein the tuning word alters a capacitive load on the crystal, thereby altering a resonant frequency thereof.

5. The method according to claim 1, wherein said calculating step evaluates substantially all available parameters to determine the valid parameters.

6. The method according to claim 1, wherein the tuning effect is determined before programming of nonvolatile memory.

7. The method according to claim 1, further comprising the step of providing a separate oscillator programming control and calculating means, and communicating the valid set of parameters between the calculating means and oscillator programming control.

8. The method according to claim 1, wherein the crystal grossly tuned.

9. The method according to claim 1, wherein the resonant frequency of the crystal is determined substantially in the absence of any final plate process tuning.

10. The method according to claim 1, wherein the algorithm comprises a phase lock loop frequency synthesis having a multiply parameter and a divide parameter for frequency translation, and wherein the valid parameters are calculated based on an intermediate tuning value, sorted by ascending divide parameter, and then evaluated in sorted order for ability of a tuning effect to null frequency error to within the error tolerance.

11. An apparatus for programming a digitally tunable oscillator, comprising:

(a) an input for receiving a desired oscillator frequency;

(b) an input for receiving an output frequency of the digitally tunable oscillator;

(c) a control for selecting a plurality of tuning states of the oscillator;

(d) a computer program for calculating valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on received output frequency of the oscillator during the plurality of tuning states; and

(e) a programmer for programming a nonvolatile memory of the oscillator with a valid set of calculated parameters.

12. The apparatus according to claim 11, wherein the apparatus also receives an input of a desired maximum error tolerance.

13. The apparatus according to claim 11, wherein the algorithm comprises a phase lock loop frequency synthesis having a multiply parameter and a divide parameter for frequency translation.

14. The apparatus according to claim 11, wherein the tuning states comprise alterations of a capacitive load on the crystal.

15. The apparatus according to claim 11, wherein said computer program evaluates substantially all available parameters to determine the valid parameters.

16. The apparatus according to claim 11, wherein the tuning states are determined before programming of the nonvolatile memory with the calculated parameters.

17. The apparatus according to claim 11, further comprising a separate oscillator programming control and calculating means, wherein the valid set of parameters are communicated between the calculating means and oscillator programming control.

18. The apparatus according to claim 11, wherein the crystal is grossly tuned.

19. The apparatus according to claim 11, wherein the resonant frequency of the crystal is determined substantially in the absence of any final plate process tuning.

20. The apparatus according to claim 11, wherein the algorithm comprises a phase lock loop frequency synthesis having a multiply parameter and a divide parameter for frequency translation, and wherein the valid parameters are calculated by the computer program based on an intermediate tuning value, sorted by ascending divide parameter, and then evaluated in sorted order for ability of a tuning effect to null frequency error to within the error tolerance.

21. A computer readable medium, containing a program for performing the steps of:

(a) receiving a desired output frequency;

(b) determining a tuning effect of a set of digital tuning words on a crystal resonant frequency;

(c) calculating valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on the determined tuning effect; and

(d) outputting at least one set of calculated valid parameters.