Apparatus and method for transmitting data serially for use with an advanced technology attachment packet interface (atapi)

• US 6,388,590 B1
• Filed: 09/24/1999
• Issued: 05/14/2002
• Est. Priority Date: 09/24/1999
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Oak Technology Partners (Qualcomm, Inc.)
• Inventors: Ng, Alan K.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US09/405,693
• Time in Patent Office: 963 Days
• Field of Search: 341/100, 341/101, 701/52, 701/57, 369/54, 369/60, 710/71, 710/52, 710/60, 370/364, 370/365, 370/366
• US Class Current: 341/100
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A transmission interface compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals are single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals are also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus. The third set of signals are serial to one another, and use low voltage level, differential signaling. Thus, the third set of signal are suited for transmission by the serial bus, which includes many fewer wires than available in an IDE bus while operating at a faster data rate.

Claims

1. A transmission interface in a first device including an Advanced Technology Attachment Packet Interface (ATAPI) for interfacing to a serial bus, the transmission interface comprising:

a. a transmission ATAPI circuit coupled to the ATAPI generating a first set of signals representative of a change in contents of the ATAPI, the first set of signals being parallel to one another, and using Transistor-Transistor Logic (TTL) voltage levels and single-ended signaling;

b. a packetizing circuit packetizing the first set of signals to generate a second set of signals representing a packet, the packet having a payload representing the change in the contents of the ATAPI, the second set of signals being parallel to one another and using TTL voltage levels and single-ended signaling; and

c. a converter converting the second set of signals into a third set of signals, the third set of signals being coupled to the serial bus, the third set of signals being serial to one another, and using low voltage level, differential signaling and being capable of being transmitted using fewer wires than available in an IDE bus, the converter supporting a faster data rate than an IDE bus.

2. The transmission interface of claim 1 wherein the transmission ATAPI circuit comprises a transmission ATAPI state machine.

3. The transmission interface of claim 2 wherein the transmission ATAPI state machine comprises a memory storing data representing transmitter ATAPI states.

4. The transmission interface of claim 3 wherein the transmission ATAPI state machine is configured to include:

a first state determining whether change has occurred in a first set of bits stored in a first register of the ATAPI, the first register being associated with a first payload type;

a second state determining whether change has occurred in a second set of bits stored in a second register of the ATAPI, the second register being associated with a second payload type; and

a third state generating the third set of signals to represent the change in one of the first set and second set of bits and to represent whether the change is associated with the first or second payload type.

5. The transmission interface of claim 4 wherein the packetizing circuit uses the payload type of the payload to generate the second set of signals.

6. The transmission interface of claim 1 wherein the converter couples the third set of signals to only two data lines.

7. The transmission interface of claim 1 wherein the converter supports a transfer data rate of 100 Mbytes/sec.

8. The transmission interface of claim 1 wherein the converter supports a transfer data rate greater than 66 Mbytes/sec.

9. A transmission interface in a first device including an Advanced Technology Attachment Packet Interface (ATAPI) for interfacing to a serial bus, the transmission interface comprising:

a. a transmission ATAPI circuit coupled to the ATAPI generating a first set of signals representative of a change in contents of the ATAPI, the first set of signals being parallel to one another, and using Transistor-Transistor Logic (TTL) voltage levels and single-ended signaling;

b. a packetizing circuit packetizing the first set of signals to generate a second set of signals representing a packet, the packet having a payload representing the change in the contents of the ATAPI, the second set of signals being parallel to one another and using TTL voltage levels and single-ended signaling; and

c. a converter converting the second set of signals into a third set of signals, the third set of signals being coupled to the serial bus, the third set of signals being serial to one another, and using low voltage level, differential signaling and being capable of being transmitted using fewer wires than available in an IDE bus, the converter supporting a faster data rate than an IDE bus;

wherein the converter supports a transfer rate at least twice that of the IDE bus.

10. The transmission interface of claim 9 wherein the converter couples the third set of signals to two wires of the serial bus.

11. The transmission interface of claim 9 wherein the converter supports a transfer rate of 100 Mbytes/sec.

12. The transmission interface of claim 9 wherein the converter supports a data rate greater than 66 Mbytes/sec.

13. A method of interfacing between an Advanced Technology Attachment Packet Interface (ATAPI) in a first device and a serial bus coupled between the first device and a second device, the method comprising:

a. detecting a change in a content of a task file of the ATAPI;

b. generating a first set of signals to represent the change in the content of the task file, the first set of signals being single-ended and parallel to one another, and using Transistor-Transistor Logic (TTL) voltage level signaling;

c. generating a second set of signals to represent in a packet format the first set of signals, the second set of signals being single-ended and parallel to one another and using TTL voltage level signaling;

d. converting the second set of signals into a third set of signals, the third set of signals being serial to one another, differential, and using low voltage level signaling; and

e. coupling the third set of signals to the serial bus, the serial bus allowing a data rate of the third set of signals to be increased without increasing a number of lines of the serial bus.

14. The method of claim 13 further comprising determining a payload type of the change of the content of the task file and wherein the payload type is used to generate the second set of signals.

15. The method of claim 13 wherein converting the second set of signals into the third set of signals includes coupling the third set of signals to the serial bus at a rate greater than 100 Mbytes/sec.

16. The method of claim 13 wherein converting the second set of signals into the third set of signals includes coupling the third set of signals to the serial bus at a rate greater than 66 Mbytes/sec.

17. The method of claim 13, wherein the third set of signals are coupled to the serial bus using only two serial data lines.

18. A transmission interface in a first device including an Advanced Technology Attachment Packet Interface (ATAPI) for interfacing to a bus, the transmission interface comprising:

an ATAPI transmission circuit for transferring a first parallel set of signals from the ATAPI; and

a converter converting the first parallel set of signals received from the ATAPI transmission circuit into a second serial, packetized set of signals;

wherein the second serial, packetized set of signals are adapted to be transmitted on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) Bus.

19. The transmission interface of claim 18, wherein the second serial, packetized set of signals contain a payload representative of the first parallel set of signals.

20. The transmission interface of claim 18, wherein the converter includes a packetizing circuit which packetizes the first parallel set of signals to generate the second serial, packetized set of signals.

21. The transmission interface of claim 18, wherein the second serial, packetized set of signals use Low-Voltage Differential Signaling (LVDS) and the first parallel set of signals use Transistor-Transistor Logic (TTL) single-ended signaling.

22. The transmission interface of claim 21, wherein the converter further converts the TTL single-ended signaling of the first parallel set of signals to the LVDS of the second serial, packetized set of signals.

23. The transmission interface of claim 18, wherein the bus includes only two data lines.

24. A transmission interface in a first device, the transmission interface comprising:

a parallel interface to an Advanced Technology Attachment Packet Interface (ATAPI);

a serial interface to a bus; and

a converter which converts a first set of parallel signals received from the parallel interface to the ATAPI to a second set of serial signals to be transmitted over the serial interface to the bus.

25. The transmission interface of claim 24, wherein the second set of serial signals are transmitted on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) Bus.

26. The transmission interface of claim 24, further including a packetizing circuit which packetizes the first set of parallel signals to generate the second set of serial signals as a set of packetized serial signals.

27. The transmission interface of claim 26, wherein the second set of packetized serial signals contains a payload representative of the first set of parallel signals.

28. The transmission interface of claim 24, wherein the first set of parallel signals uses Transistor-Transistor Logic (TTL) single-ended signaling, and the second set of serial signals uses Low-Voltage Differential Signaling (LVDS).

29. The receiver interface of claim 24, wherein the bus includes only two data lines.