Distributed type switching system

• US 6,389,025 B2
• Filed: 06/05/2001
• Issued: 05/14/2002
• Est. Priority Date: 09/16/1986
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kato, Takao, Kuwahara, Hiroshi, Gohara, Shinobu, Sakurai, Yoshito, Ohtsuki, Kenichi, Amada, Eiichi
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): HOM, SHICK C
• Application Number:
  US09/873,280
• Publication Number:
  US 20010028658A1
• Time in Patent Office: 343 Days
• Field of Search: 370/354, 370/355, 370/369, 370/370, 370/378, 370/380, 370/387, 370/396, 370/398, 370/400, 370/414, 370/416, 370/418, 370/427
• US Class Current: 370/396
• CPC Class Codes: H04J 2203/0012 Switching modules and their interconnections
• CPC Class Codes: H04L 12/56 Packet switching systems
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 2012/6481 Speech, voice
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/106 using space switching, e.g. crossbar or matrix
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/1553 Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/1584 Full Mesh, e.g. knockout
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/256 Routing or path finding in ATM switching fabrics
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3018 : Input queuing
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/309 : Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/35 : Switches specially adapted for specific applications
• CPC Class Codes: H04Q 11/0407 : using a stored programme control
• CPC Class Codes: H04Q 11/0421 : Circuit arrangements therefor
• CPC Class Codes: H04Q 11/06 : Time-space-time switching

Abstract

A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Claims

1. A packet switching system comprising:

a plurality of first modules, wherein each first module, when a destination of information received from a first interface of said each first module is another first module, converts said received information to a fixed-length packet having a header and an information field and outputs said fixed-length packet to its second interface;

a second module having a space switch which interconnects said plurality of first modules, wherein said second module operates to receive said fixed-length packet from said second interface of said each first module and output the received fixed-length packet to a second interface of said another first module which is a destination of said information received from the first interface; and

a collision preventing circuit which controls information transmission and reception timings among said plurality of first modules and said second module so that fixed-length packets transmitted among said plurality of first modules and said second module do not collide against each other in said second module.

2. The packet switching system according to claim 1, wherein transfer of fixed-length packet among said plurality of first modules and said second module is performed by multiplexing said fixed-length packet on a predetermined frame and said collision preventing circuit controls an input timing of said fixed-length packet to said space switch.

3. A packet switching system comprising:

a plurality of first modules, wherein each first module has a memory which stores information received from a first interface of said each first module and a controller, and when a destination of said received information is another first module, converts said information received from the first interface to a fixed-length packet having a header and an information field and outputs said fixed-length packet from its second interface;

a second module having a space switch which interconnects said plurality of first modules, wherein said second module operates to receive said fixed-length packet from said second interface of said each first module and output the received fixed-length packet to a second interface of said another first module which is the destination of said information received from the first interface; and

a collision preventing circuit which controls information transmission and reception timings among said plurality of first modules and said second module so that fixed-length packets transmission among said plurality of first modules and said second module do not collide against each other in said second module.

4. The packet switching system according to claim 3, wherein transfer of fixed-length packet among said plurality of first modules and said second module is performed by multiplexing said fixed-length packet on a predetermined frame and said collision preventing circuit controls an input timing of said fixed-length packet to said space switch.

5. A packet switching system comprising:

a plurality of first modules, wherein each first module converts, based on a destination of information received from a incoming line of said each first module, said received information to a fixed-length packet having a header and an information field and outputs said fixed-length packet to an internal line of said each first module from among a plurality of internal lines;

a second module having a space switch which transfers said fixed-length packet among said plurality of internal lines, wherein said second module operates to receive said fixed-length packet from said internal line of said each first module and output the received fixed-length packet to an internal line coupled to one of a plurality of third modules which is the destination of said information received from the internal line;

said plurality of third modules each of which converts a fixed-length packet received from said internal line to information received by said incoming line and outputs said information to one of outgoing lines which is the destination of said instruction received from said each first module; and

a collision preventing circuit which controls information transmission and reception timings among said first modules and said second module so that fixed length packets transmitted among said plurality of first modules and plurality of third modules do to collide against each other in said second module.

6. The packet switching system according to claim 5, wherein transfer of fixed-length packet among said plurality of first modules, second module and plurality of third modules is performed by multiplexing said fixed-length packet on a predetermined frame and said collision preventing circuit controls an input timing of said fixed length packet to said space switch.

7. A packet switching system comprising:

a plurality of first modules, wherein each first module has a first memory which stores information received from an incoming line of said each first module and a controller and, based on a destination of said information received from the incoming line, converts said information received from the incoming line to a fixed-length packet having a header and an information field and outputs said fixed-length packet to an internal line of said each first module from among a plurality of internal lines;

a second module having a space switch which transfers said fixed-length packet among said plurality of internal lines, wherein said second module operates to receive said fixed-length packet from said internal line of said each first module and output the received fixed-length packet to one of the internal line which is connected to one of a plurality of third modules which is the destination of said information received from the incoming line; and

said plurality of third modules each of which has a second memory for storing fixed-length packet received from said internal line and a second controller, converts said received fixed-length packet to said information received by said incoming line and outputs said information to one of outgoing lines which is the destination of said information; and

a collision preventing circuit which controls information transmission and reception timings among said first modules and said second module so that fixed-length packets transmitted between said plurality of first modules and said plurality of third modules do not collide against each other in said second module.

8. The packet switching system according to claim 7, wherein transfer of fixed-length packet among said plurality of first modules, said second module and said plurality of third modules is performed by multiplexing said fixed-length packet on a predetermined frame and said collision preventing circuit controls an input timing of said fixed-length packet to said space switch.

9. A packet switching system comprising:

a plurality of first modules, wherein each first module converts when a destination of information received from the first incoming line of said each first module is another first module, said information received from the first incoming line to a fixed-length packet having a header and an information field and outputs said fixed-length packet to its internal line from among a plurality of internal lines;

a second module having a space switch which interconnects said plurality of first modules, wherein said second module operates to receive said fixed-length packet from one of said plurality of internal lines and output the received fixed-length packet to one of said plurality of internal lines which is connected to said another first module which is the destination of said information received from the first incoming line; and

a collision preventing circuit which controls information transmission and reception timings among said plurality of first modules and said second module so that fixed-length packets transmitted among said plurality of first modules and said module do not collide against each other in said second module.

10. The packet switching system according to claim 9, wherein transfer of fixed-length packet among said plurality of first modules and second module is performed by multiplexing said fixed-length packet on a predetermined frame and said collision preventing circuit controls an input timing of said fixed-length packet to said space switch.

11. A packet switching system comprising:

a plurality of first modules, wherein each first module having a memory which stores information received from an incoming line of said each first module and a controller, when a destination of said information received from the incoming line is another first module, converts said information received from the incoming line to a fixed-length packet having a header and an information field and outputs said fixed-length packet to an internal line of said each first module from among a plurality of internal lines;

a second module having a space switch which interconnects said plurality of first modules, wherein said second module operates to receive said fixed-length packet from one of said plurality of internal lines and output the received fixed-length packet to one of said plurality of internal lines which is coupled to said another first module which is the destination of said information received from the incoming line; and

a collision preventing circuit which controls information transmission and reception timings among said plurality of first modules and said second module so that fixed-length packets transmitted among said plurality of first modules and second module do not collide against each other in said second module.

12. The packet switching system according to claim 11, wherein transfer of fixed-length packet among said plurality of first modules and second module is performed by multiplexing said fixed-length packet on a predetermined frame and said collision preventing circuit controls an input timing of said fixed-length packet to said space switch.

13. A packet switching system comprising:

a plurality of first modules, wherein each first module, when a destination of information received from an incoming line is another first module, converts said information received from the incoming line to a fixed-length packet and outputs said fixed-length packet to an internal line of said each first module from among a plurality of internal lines;

a second module having a space switch which interconnects said plurality of first modules, wherein said second module operates to receive said fixed-length packet from one of said plurality of internal lines and output the received fixed-length packet to one of said plurality of internal lines which is connected to said another first module which is the destination of said information received from the incoming line; and

a collision preventing circuit which controls information transmission and reception timings among said plurality of first modules and said second modules so that fixed-length packets transmitted among said plurality of first modules and said second module do not collide against each other in said second module.

14. The packet switching system according to claim 13, wherein each first module has a memory for storing information received from its incoming line and a controller and converts said received information to said fixed-length packet.