Translation hardware assist for data communication switch

• US 6,389,035 B1
• Filed: 05/08/1998
• Issued: 05/14/2002
• Est. Priority Date: 05/08/1998
• Status: Expired due to Term

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Alcatel Internetworking Incorporated (Nokia Corporation)
• Inventors: Narsinh, Anees, Bertagna, Drew
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): JONES, PRENELL P
• Application Number:
  US09/075,299
• Time in Patent Office: 1,467 Days
• Field of Search: 370/236, 370/70, 370/480, 370/465, 370/375, 370/413, 370/429-434, 370/458, 370/229, 370/395, 370/407, 370/210, 370/442, 370/463, 370/449, 370/535, 370/473, 370/409, 370/351, 370/257, 200/84, 200/80, 710/104
• US Class Current: 370/465
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/26 using explicit feedback to the source, e.g. choke packets
• CPC Class Codes: H04L 47/36 by determining packet size, e.g. maximum transfer unit [MTU]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A protocol translation hardware assist for resolving protocol incompatibilities in a multi-protocol switching environment. Discrete information units are transferred seamlessly from inputs to disparate protocol outputs by writing inbound discrete information units into selected address spaces in allocated buffers in a transfer queue in a manner which accounts for protocol format differences while allowing for straightforward dequeueing. The hardware assist fragments inbound discrete information units into multiple outbound units and creates offsets indicated by destination protocol requirements. A bypass check may be implemented to avoid subjecting to the fragmentation inquiry discrete information units for which it can be inferred a priori that fragmentation is not required.

Claims

1. A method for assisting switching a discrete information unit of digital data, for use within a switching controller having an input interface and a plurality of output interfaces, wherein the output interfaces are associated with nodes operative in different protocols, and a transfer memory for switching the discrete information unit from an input interface to an output interface, comprising the steps of:

(a) determining a destination node for the discrete information unit;

(b) determining a segment size for the discrete information unit through association with the destination node;

(c) allocating buffers in the transfer memory to the discrete information unit; and

(d) writing the discrete information unit in the allocated buffers as a series of segments of the segment size.

2. The switching assist method according to claim 1, further comprising the steps of:

(e) formatting the written segments for the protocol type operative on the destination node; and

(f) reading the formatted written segments to the destination interface associated with the destination node.

3. The switching assist method according to claim 2, wherein the formatting step comprises writing protocol header information into address spaces preceding the written segments in the allocated buffers.

4. A method for assisting switching a discrete information unit of digital data, for use within a switching controller having an input port and a plurality of output ports, wherein the output ports are operative in different protocols, and a transfer memory for switching the discrete information unit from a source input port to a destination output port, comprising the steps of:

(a) determining a destination output port for the discrete information unit and one or more translation assist values for the destination output port, the translation assist values including a maximum transfer unit value identifying a maximum length for a unit for transmission on the destination output port and a segment size value identifying an allowable length for a unit for transmission on the destination output port;

(b) comparing the length of the discrete information unit with the maximum transfer unit value; and

(c) if the length of the discrete information unit exceeds the maximum allowable length, writing the discrete information unit to the transfer memory as a series of segments of the segment size, the written segments separated from one another by an amount of address space; and

(d) otherwise, writing the discrete information unit to the transfer memory as a single contiguous segment.

5. The switching assist method according to claim 4, wherein the translation assist values further include a header offset value, and wherein each written segment is preceded in memory by a skipped address space of a size indicated by the header offset value.

6. The switching assist method according to claim 5, wherein header information for a written segment is constructed in at least part of a skipped address space.

7. The switching assist method according to claim 6, further comprising:

(e) repeating steps (a) through (d) for a plurality of discrete information units; and

(f) reading pairs of headers and segments from the transfer memory to the destination output ports in a predetermined logical order.

8. The switching assist method according to claim 4, wherein the destination output port is determined by association with an identifier in the discrete information unit.

9. The switching assist method according to claim 4, wherein the translation assist values are determined by association with the determined destination output port.

10. The switching assist method according to claim 4, wherein the translation assist values are stored in a register maintained for the protocol type operative on the destination output port.

11. A method for assisting switching a discrete information unit of digital data, for use within a switching controller having an input port and a plurality of output ports, wherein the output ports are operative in different protocols, and a transfer memory for switching the discrete information unit from a source input port to a destination output port, comprising the steps of:

(a) determining a destination output port for the discrete information unit and one or more translation assist values for the protocol type operative on the destination output port, the translation assist values including a maximum transfer unit value identifying a maximum length for a unit of the protocol type and a segment size value identifying an allowable length for a unit of the protocol type;

(b) comparing the length of the discrete information unit with the maximum transfer unit value; and

(c) if the length of the discrete information unit exceeds the maximum allowable length, writing the discrete information unit to the transfer memory as a series of segments of the segment size, the written segments separated from one another by an amount of address space; and

(d) otherwise, writing the discrete information unit to the transfer memory as a single contiguous segment.

12. The switching assist method according to claim 11, wherein the translation assist values further include a header offset value, and wherein each written segment is preceded in memory by a skipped address space of a size indicated by the header offset value.

13. The switching assist method according to claim 12, wherein header information for a written segment is constructed in at least part of a skipped address space.

14. The switching assist method according to claim 13, further comprising:

(e) repeating steps (a) through (d) for a plurality of discrete information units; and

(f) reading pairs of headers and segments from the transfer memory to the destination output port in a predetermined logical order.

15. The switching assist method according to claim 11, wherein the destination output port is determined by association with an identifier in the discrete information unit.

16. The switching assist method according to claim 11, wherein the translation assist values are determined by association with the determined destination output port.

17. The switching assist method according to claim 11, wherein the translation assist values are stored in a register maintained for the protocol type operative on the destination output port.

18. A method for assisting switching a discrete information unit of digital data, for use within a switching controller having an input port and a plurality of output ports, wherein the output ports are operative in different protocols, and a transfer memory for switching the discrete information unit from a source input port to a destination output port, comprising the steps of:

(a) comparing the protocol type of the inbound discrete information unit with a configured protocol type value, the configured value identifying the protocol type which among all protocol types active on any output port specifies the shortest maximum length for a unit for transmission in the protocol type; and

(b) if the inbound discrete information unit is of the identified protocol type, writing the discrete information unit in the transfer memory as a single contiguous segment;

(c) otherwise,

(i) determining a destination output port for the discrete information unit and one or more translation assist values for the destination output port, the translation assist values including a maximum transfer unit value identifying a maximum length for a unit for transmission on the destination output port and a segment size value identifying an allowable length for a unit for transmission on the destination output port;

(ii) comparing the length of the discrete information unit with the maximum transfer unit value; and

(iii) if the length of the discrete information unit exceeds the maximum allowable length, writing the discrete information unit in the transfer memory as a series of segments of the segment size, the written segments separated from one another by an amount of address space; and

(iv) otherwise, writing the discrete information unit in the transfer memory as a single contiguous segment.

19. The switching assist method according to claim 18, wherein each segment written pursuant to step (b) is preceded by a skipped address space of a size which corresponds to a header offset value for the protocol type which specifies the largest header offset among all protocol types active on any output port.

20. The switching assist method according to claim 19, wherein header information for a written segment is constructed in at least part of a skipped address space.

21. The switching assist method according to claim 18, wherein the translation assist values further include a header offset value, and wherein each segment written pursuant to step (c) is preceded by a skipped address space of a size indicated by the header offset value.

22. The switching assist method according to claim 21, wherein a header for a written segment is constructed in at least part of a skipped address space.

23. The switching assist method according to claim 18, further comprising:

(e) repeating steps (a) through (c) for a plurality of discrete information units; and

(f) reading pairs of headers and segments from the transfer memory to the destination output ports in a predetermined logical order.