Synchronization and tracking in a digital communication system

• US 6,389,088 B1
• Filed: 02/22/2000
• Issued: 05/14/2002
• Est. Priority Date: 04/17/1997
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: ITT Manufacturing Enterprises, Inc. (ITT, Inc.)
• Inventors: Blois, Gary Vincent, Fine, Joseph Michael, Epstein, Marvin A.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US09/510,496
• Time in Patent Office: 812 Days
• Field of Search: 375/225, 375/226, 375/227, 375/145, 375/149, 375/280, 375/281, 375/325, 375/326, 375/331, 375/332, 375/343, 375/355, 375/366, 375/367, 375/368, 375/369, 370/510, 370/511, 370/515, 329/304
• US Class Current: 375/355
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

There is disclosed a bit sync search and frame sync search system operative with a digital data signal as transmitted by a digital radio transmitter. The bit search is implemented by detecting a predetermined phasing signal which is incorporated in the digital signal and which has a repetitive bit pattern of ones and zeroes. The phasing signal is first detected by providing an in-phase and quadrature component signal and correlating those signals to provide an output signal indicative of the bit pattern in the phasing signal. After the phasing signal has been provided and an oscillator associated with a receiving apparatus is compensated according to the detected phasing signal, a tracking mode is entered, whereby a frame signal is captured and the system generates histograms of data bit transitions for producing an error signal indicative of the difference of the transmitted clock rate and the sampling portion of a received bit. In this manner, by adjusting the clock according to the error signal produced by the histogram process one can be assured that the sampling rate at the receiver will occur relatively at the center of each bit to therefore provide reliable decoding or detection of the received digital data signal in the presence of the noise.

Claims

1. In a receiver of a digital communication system, a method of detecting a periodic synchronization signal having a bit synchronization pattern, the method comprising the steps of:

(a) accumulating a set of samples during a frame;

(b) computing an inphase correlation value and a quadrature correlation value for the set of samples;

(c) computing a partial power for the set of samples;

(d) repeating steps (a), (b) and (c) for a plurality of frames;

(e) computing an inphase sum from the inphase correlation values of the plurality of frames and a quadrature sum from the quadrature correlation values of the plurality of frames;

(f) computing a signal power as the sum of the squares of the inphase sum and quadrature sum;

(g) computing a total power as the sum of the partial powers of the plurality of frames; and

(h) declaring a detection of the periodic synchronization signal by said receiver if the signal power is above a minimum threshold and greater than a required percentage of the total power.

2. The method of claim 1, wherein step (b) includes:

(b1) calculating the inphase correlation value as a sum of the samples weighted by inphase coefficients whose values vary in accordance with the period of the bit synchronization pattern; and

(b2) calculating the quadrature correlation value as a sum of the samples weighted by quadrature coefficients whose values vary in accordance with the period of the bit synchronization pattern and are 90°

out of phase with the inphase coefficients.

3. The method of claim 1, further comprising the steps of:

(i) calculating a bit phase error from the inphase sum and the quadrature sum to determine a bit edge time;

(j) coarsely correcting the bit phase error by moving a sample pointer to a sample closest to the bit edge time, thereby reducing the bit phase error to a resultant fractional sample error; and

(k) finely correcting the bit phase error by adjusting a rubber clock in accordance with the resultant fractional sample error.

4. A digital communication system, comprising:

a transmitter configured to transmit a periodic synchronization signal having a bit synchronization pattern; and

a receiver configured to detect the periodic synchronization signal, said receiver comprising;

an analog-to-digital (A/D) converter that periodically samples data bits of a received signal to accumulate a set of samples for each of a plurality of frames; and

a processor adapted to compute;

an inphase correlation value, a quadrature correlation value and a partial power for each frame from the set of samples corresponding to the frame;

an inphase sum from the inphase correlation values of the plurality of frames;

a quadrature sum from the quadrature correlation values of the plurality of frames;

a signal power as the sum of the squares of the inphase sum and quadrature sum; and

a total power as the sum of the partial powers of the plurality of frames;

said processor declaring a detection of the periodic synchronization signal if the signal power is above a minimum threshold and greater than a required percentage of the total power.

5. The system of claim 4, wherein said processor calculates the inphase correlation value as a sum of the samples weighted by inphase coefficients whose values vary in accordance with the period of the bit synchronization pattern, and calculates the quadrature correlation value as a sum of the samples weighted by quadrature coefficients whose values vary in accordance with the period of the bit synchronization pattern and are 90°

out of phase with the inphase coefficients.

6. The system of claim 4, wherein said processor calculates a bit phase error from the inphase sum and the quadrature sum to determine a bit edge time, said receiver coarsely correcting the bit phase error by moving a sample pointer to a sample closest to the bit edge time, thereby reducing the bit phase error to a resultant fractional sample error, said receiver finely correcting the bit phase error by adjusting a rubber clock in accordance with the resultant fractional sample error.