Converification system and method

• US 6,389,379 B1
• Filed: 06/12/1998
• Issued: 05/14/2002
• Est. Priority Date: 05/02/1997
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Axis Systems Incorporated (Cadence Systems, Inc.)
• Inventors: Tseng, Ping-Sheng, Lin, Sharon Sheau-Pyng
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US09/096,865
• Time in Patent Office: 1,432 Days
• Field of Search: 395/500.38, 395/500.42, 395/500.49, 395/500.44, 395/500.36, 395/500.37, 703/14, 703/23, 716/5
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device. The user may decide to use actual I/O devices as well as modeled I/O devices in one debug session. The software clock is used as the external clock source for the target system and the external I/O devices to synchronize all data that is delivered between the coverification system and the external interface. The coverification system contains a control logic that provides traffic control between: (1) the RCC computing system and the RCC hardware array, and (2) the external interface (which are coupled to the target system and the external I/O devices) and the RCC hardware array. Because the RCC computing system has the model of the entire design in software, including that portion of the user design modeled in the RCC hardware array, the RCC computing system must also have access to all data that passes between the external interface and the RCC hardware array. The control logic ensures that the RCC computing system has access to these data. Pointers are used to latch data from the RCC computing system and the external interface to the internal nodes of the hardware model in the RCC hardware array. Pointers are also used to deliver data from the internal nodes of the hardware model to the RCC computing system and the external interface. Even if the data from the internal nodes of the hardware model is intended for the external interface, the RCC computing system must also be able to access this data as well.

Claims

1. A coverification system for verifying a user design, comprising:

a computing system including a central processing unit and memory for modeling the user design in software for simulating the user design;

an internal bus system coupled to the computing system;

reconfigurable hardware logic coupled to the internal bus system and for modeling at least a portion of the user design in hardware;

an external interface coupled to the internal bus system and at least one external device; and

control logic coupled to the internal bus system for controlling the delivery of data among the reconfigurable hardware logic, the computing system, and the external interface.

2. The coverification system of claim 1, wherein the control logic further comprises:

a data-in control logic for controlling delivery of data from the computing system and the external interface to the reconfigurable hardware logic, including

data-in pointer logic coupled to the internal bus system for generating selective pointer signals to a data-in latch logic, the generation of selective pointer signals based on whether the data is arriving from the computing system or the external interface and the particular internal nodes in the reconfigurable hardware logic selected to be driven, and

data-in latch logic coupled to the internal bus system, a plurality of internal nodes in the reconfigurable hardware logic, and the data-in pointer logic for delivering data from the internal bus system to selective internal nodes in the reconfigurable hardware logic in response to the selective pointer signals.

3. The coverification system of claim 2, further comprising:

an external buffer coupled to the external interface for storing data originating from the external interface and also coupled to the internal bus system the computing system has access to data in the external buffer.

4. The coverification system of claim 2, wherein the control logic further comprises:

a data-out control logic for controlling delivery of data from the reconfigurable hardware logic to the computing system and the external interface, including,

data-out pointer logic coupled to the internal bus system for generating selective pointer signals to a data-out gating logic, the generation of selective pointer signals based on whether the data is destined for the computing system or the external interface and the particular internal nodes in the reconfigurable hardware logic selected to be driven, and

data-out gating logic coupled to the internal bus system, a plurality of internal nodes in the reconfigurable hardware logic, and the data-out pointer logic for delivering data from the selective internal nodes in the reconfigurable hardware logic to the internal bus system in response to the selective pointer signals.

5. The coverification system of claim 1, further comprising:

software clock logic for detecting an active clock edge of a clock signal in the software model during data evaluation, generating a software clock to the reconfigurable hardware logic to control a corresponding data evaluation in the reconfigurable hardware logic, and generating the software clock to the external interface.

6. The coverification system of claim 1, wherein the computing system further includes at least one model of an external I/O device in software.

7. A method of verifying the proper operation of a user design connected to an external I/O device, comprising steps:

generating a first model of the user design in software for simulating the user design;

generating a second model of at least a portion of the user design in hardware; and

controlling the second model in hardware with the first model in the software.

8. The method of claim 7, wherein the step of controlling further comprises:

synchronizing the data evaluation in the first model in software and the second model in hardware with a software-generated clock.

9. The method of claim 8, further comprising steps:

simulating selected debug test points in software;

accelerating selected debug test points in hardware; and

controlling the delivery of data among the first model in software, the second model in hardware, and the external I/O device so that the first model in software has access to all delivered data.

10. The method of claim 9, wherein the step of controlling further comprising steps:

selecting at least one internal node in the reconfigurable hardware logic;

determining if the data being delivered is from the first model in software or the external I/O device; and

generating selected pointer signals to at least one latching logic coupled to the selected internal node based on the selecting and determining steps so that the data is delivered from either the first model in software or the external I/O device to the second model in hardware.

11. The method of claim 10, further comprising steps:

storing data delivered from the external I/O device in an external buffer coupled to the second model in hardware; and

providing the first model in software access to data in the external buffer.

12. The method of claim 9, wherein the step of controlling further comprising steps:

selecting at least one internal node in the reconfigurable hardware logic;

determining if the data being delivered is destined for the first model in software or the external I/O device; and

generating selected pointer signals to at least one gating logic coupled to the selected internal node based on the selecting and determining steps so that the data is delivered from the second model in hardware to either the first model in software or to both the first model in software and the external I/O device.

13. The method of claim 7, further comprising step:

generating a model of an external I/O device in software.

14. A method of transporting data with a coverification tool in a computing environment for verifying the proper operation of a user design, the computing environment having a computing system which includes a first model of the user design in software for simulating the user design, a reconfigurable hardware logic which includes a second model of at least a portion of the user design in hardware, and an external I/O device, comprising steps:

delivering a first data from the computing system to the reconfigurable hardware logic; and

delivering the first data from the computing system to a software clock logic for generating a software clock to the reconfigurable hardware logic and the external I/O device.

15. The method of claim 14, further comprising steps:

delivering a second data from the external I/O device to the reconfigurable hardware logic.

16. The method of claim 15, wherein the reconfigurable hardware logic includes a plurality of reconfigurable logic elements, further comprising steps:

determining internal nodes in each reconfigurable logic element that need to be driven by a third data; and

delivering the third data sequentially from the computing system to each selected internal node in each reconfigurable logic element in the reconfigurable hardware logic, one selected internal node at a time.

17. The method of claim 14, wherein the reconfigurable hardware logic includes a plurality of reconfigurable logic elements, further comprising steps:

delivering a fourth data from a first reconfigurable logic element to the computing system; and

delivering a fifth data from the first reconfigurable logic element to the computing system and the external I/O device.