Method and apparatus for calculating delay times in semiconductor circuit

• US 6,389,381 B1
• Filed: 03/09/1998
• Issued: 05/14/2002
• Est. Priority Date: 06/13/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Rieko, Yoneda, Takashi, Isoda, Masahito
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US09/037,063
• Time in Patent Office: 1,527 Days
• Field of Search: 703/2, 703/13, 703/19, 703/14, 702/29, 716/6
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and apparatus for calculating circuit delay times efficiently arranges and stores data to reduce system memory requirements, which allows computers without large storage devices, such as conventional personal computers with limited hard disk space, to be used for testing preliminary device designs, Delay time ratio coefficient values representing a ratio of a delay time determined by values of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element are stored in a coefficient table. The dependency factors include process condition, in use or operational temperature, and first and second operational supply voltages.

Claims

1. A method of computing delay times of circuit elements of a semiconductor device, comprising:

preparing at least two coefficient tables storing a plurality of delay time ratio coefficient values, one of which being a first delay time ratio coefficient value, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors having a close correlation with one another to a predetermined reference delay time of a circuit element, the first coefficient table having a first matrix table of the plurality of delay time ratio coefficient values respectively associated with the plurality of dependency factors, one of which being a first dependency factor, and the second coefficient table having a second matrix table of the first delay time ratio coefficient value and a second delay time ratio coefficient value, the first delay time ratio coefficient value being associated with the first dependency factor, and the second delay time ratio coefficient value being associated with a second dependency factor having a close correlation with the first dependency factor;

acquiring at least one of the delay time ratio coefficient values from the first coefficient table and acquiring at least one of the first and second delay time ratio coefficient values from the second coefficient table;

computing a delay time of a circuit element using the acquired delay time ratio coefficient values and a reference delay time; and

performing a circuit timing simulation using the delay time.

2. The method according to claim 1, wherein the semiconductor device having a first circuit element for receiving a first operational supply voltage as the first dependency factor, and a second circuit element for receiving the first operational supply voltage and a second operational supply voltage as the second dependency factor, the method further comprising:

preparing a first equation used in computing a delay time of the first circuit element and a second equation used in computing a delay time of the second circuit element;

generating a functional model in which identification data for identifying the first and second circuit elements based on the first and second dependency factors are described; and

selecting one of the first and second equations in accordance with the identification data of the functional model.

3. The method according to claim 2, wherein the functional model having a delay time model of the circuit element in which identification data are described.

4. The method according to claim 2, wherein the functional model having a logic model in which identification data are described and in which a function and operation of the circuit element are equivalently represented.

5. The method according to claim 1, wherein the dependency factors having a process condition of the semiconductor device, a temperature of the semiconductor device while in use and first and second operational supply voltages supplied to the semiconductor device;

and

the first coefficient table stores the plurality of delay time ratio coefficient values associated with the process condition, the temperature in use and a value of the first operational supply voltage and the second coefficient table stores the first and second delay time ratio coefficient values respectively associated with values of the first and second operational supply voltages.

6. An apparatus for computing delay times of circuit elements of a semiconductor device, comprising:

at least two coefficient tables storing a plurality of delay time ratio coefficient values, one of which being a first delay time ratio coefficient value, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors having a close correlation with one another to a predetermined reference delay time of a circuit element, said first coefficient table having a first matrix table of the plurality of delay time ratio coefficient values respectively associated with the plurality of dependency factors, one of which being a first dependency factor and said second coefficient table including a second matrix table of the first delay time ratio coefficient value and a second delay time ratio coefficient value, the first delay time ratio coefficient value being associated with the first dependency factor, and the second delay time ratio coefficient value being associated with a second dependency factor having a close correlation with the first dependency factor;

a processing unit for acquiring at least one of the delay time ratio coefficient values from said first coefficient table, acquiring at least one of the first and second delay time ratio coefficient values from said second coefficient table, and computing a delay time of a circuit element using the acquired delay time ratio coefficient values and a reference delay time; and

performing a circuit timing simulation using the delay time.

7. The apparatus according to claim 6, wherein:

the semiconductor device having a first circuit element for receiving a first operational supply voltage as the first dependency factor, and a second circuit element for receiving the first operational supply voltage and a second operational supply voltage as the second dependency factor;

said processing unit computes the delay time of the first circuit element according to a first equation and computes the delay time of the second circuit element according to a second equation; and

the apparatus further comprising a storage structure for storing a functional model in which identification data for identifying the first and second circuit elements based on the first and second dependency factors are described, wherein said processing unit selects one of the first and second equations in accordance with the identification data of the functional model.

8. The apparatus according to claim 6, wherein the dependency factors having a process condition of the semiconductor device, a temperature of the semiconductor device while in use and first and second operational supply voltages supplied to the semiconductor device;

and

said first coefficient table stores the plurality of delay time ratio coefficient values associated with the process condition, the temperature in use and a value of the first operational supply voltage and said second coefficient table stores the first and second delay time ratio coefficient values respectively associated with values of the first and second operational supply voltages.

9. A method of generating at least two coefficient tables for use in computing delay times of circuit elements of a semiconductor device, comprising:

computing a plurality of delay time ratio coefficient values, having first and second delay time ratio coefficient values, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors, one of which being a first dependency factor, the dependency factors having a close correlation with one another to a predetermined reference delay time of a circuit element;

storing the plurality of delay time ratio coefficient values in the first coefficient table;

storing the first and second delay time ratio coefficient values in the second coefficient table, the first delay time ratio coefficient value being associated with the first dependency factor, and the second delay time ratio coefficient value being associated with a second dependency factor having a close correlation with the first dependency factor;

computing a delay time of a circuit element using the delay time ratio coefficient values; and

performing a circuit timing simulation using the delay time.

10. A storage product including a recording medium where a computer readable program code for computing delay times of circuit elements of a semiconductor device is recorded therein, the program executing processes for:

preparing at least two coefficient tables storing a plurality of delay time ratio coefficient values having a first delay time ratio coefficient value, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors having a close correlation with one another to a predetermined reference delay time of a circuit element, the first coefficient table having a first matrix table of the plurality of delay time ratio coefficient values respectively associated with the plurality of dependency factors having a first dependency factor and the second coefficient table having a second matrix table of the first delay time ratio coefficient value and a second delay time ratio coefficient value, the first delay time ratio coefficient value being associated with the first dependency factor, and the second delay time ratio coefficient value being associated with a second dependency factor having a close correlation with the first dependency factor;

acquiring at least one of the delay time ratio coefficient values from the first coefficient table and acquiring at least one of the first and second delay time ratio coefficient values from the second coefficient table;

computing a delay time of a circuit element using the acquired delay time ratio coefficient values and a reference delay time; and

performing a circuit timing simulation using the delay time.

11. The storage product according to claim 10, wherein the semiconductor device having a first circuit element for receiving a first operational supply voltage as the first dependency factor, and a second circuit element for receiving the first operational supply voltage and a second operational supply voltage as the second dependency factor, the program further executing processes for:

preparing a first equation used in computing a delay time of the first circuit element and a second equation used in computing a delay time of the second circuit element;

generating a functional model in which identification data for identifying the first and second circuit elements based on the first and second dependency factors is described; and

selecting one of the first and second equations in accordance with the identification data of the functional model.

12. The storage product according to claim 11, wherein the functional model having a delay time model of a circuit element in which identification data are described.

13. The storage product according to claim 11, wherein the functional model having a logic model in which identification data are described and in which a function and operation of a circuit element are equivalently represented.

14. The storage product according to claim 10, wherein the dependency factors include a process condition of the semiconductor device, a temperature of the semiconductor device while in use and first and second operational supply voltages supplied to the semiconductor device;

and

the first coefficient table stores the plurality of delay time ratio coefficient values associated with the process condition, the temperature in use and a value of the first operational supply voltage and the second coefficient table stores the first and second delay time ratio coefficient values respectively associated with values of the first and second operational supply voltages.