Restore tracking system for DRAM

• US 6,389,505 B1
• Filed: 11/19/1998
• Issued: 05/14/2002
• Est. Priority Date: 11/19/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reohr, William Robert, Emma, Philip George, Wang, Li-Kong
• Primary Examiner(s): Ellis, Kevin L.
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/196,086
• Time in Patent Office: 1,272 Days
• Field of Search: 711/105, 711/106, 711/154, 365/185.25, 365/222
• US Class Current: 711/106
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure

Abstract

A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven'"'"'t been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.

Claims

1. A restore tracking system for reducing a number of refresh actions needed to maintain data entries in a DRAM, comprising:

restore tracking means for recording and updating a refresh status of one or more of said data entries in said DRAM; and

control logic means, coupled to said restore tracking means, for refreshing said one or more of said data entries having an expired status.

2. The restore tracking system of claim 1, further comprising:

said restore tracking means comprising;

a timer for tracking a time elapsed since a data entry has been refreshed; and

means for asserting a positive decoded refresh address signal once the timer has expired;

said control logic means comprising priority encode logic means for mapping said positive decoded refresh address signal to an encoded refresh address.

3. The restore tracking system of claim 2, further comprising:

multiple said restore tracking means, all of which assert a positive decoded refresh address signal once the timer has expired; and

said control logic means comprising priority encode logic for generating both an encoded refresh address, which is sent to the DRAM, and a refresh request control signal to direct a refresh of said encoded refresh address.

4. The restore tracking system of claim 3, said priority encode logic, further comprising:

means for handling multiple requests over an extended number of memory cycles using a predetermined ordering, wherein more than one said decoded refresh address signal may be positive at any given time.

5. The restore tracking system of claim 1, further comprising:

a cache memory wherein said DRAM is integrated within said cache memory.

6. The restore tracking system of claim 1, wherein said DRAM includes blocks of memory cells which are refreshed by an external means, said restore tracking system further comprising:

a plurality of restore tracking circuits, each devoted to a block of memory cells for tracking the total time elapsed since said block was last restored, and specifying a maximum data retention time of said DRAM; and

said external means comprising means for triggering a refresh of said block if said restore tracking circuit for said block reaches said maximum data retention time.

7. The restore tracking circuit of claim 1, wherein said DRAM is coupled to said restore tracking means, said DRAM including blocks of memory cells which are refreshed by naturally occurring read and write actions, said restore tracking circuit further comprising:

a timer for monitoring a total time elapsed since a block of memory was last refreshed; and

timer reset logic, coupled to the timer, for restarting said timer upon determining said block of cells has been restored by said naturally occurring read or write actions to said DRAM.

8. The restore tracking system of claim 1, further comprising:

said restore tracking means comprising a timer for tracking a time elapsed since a data entry has been refreshed;

OR logic, coupled to said restore tracking circuit, for generating an address search request if the timer expires; and

said control logic comprising search control logic means for locating an address of the expired timer, said control logic coupled to said OR logic,.

9. The restore tracking system of claim 1, further comprising:

a cache memory wherein said DRAM is integrated within said cache memory and one restore tracking means is coupled to each DRAM cache entry;

hit logic means coupled to said restore tracking means;

a directory of the DRAM cache, coupled to the hit logic and said restore tracking system, the directory holding tag address bits and directory status bits, said status bits defining whether a cache entry status is valid and whether it can be read or written; and

in response to a request for a particular address is directed to the cache, the tag address is read out of the directory and driven into the hit logic;

said hit logic means, further coupled to the directory, for comparing the tag address with a tag portion of the requested address;

wherein if the two tags match, a cache hit is said to have occurred in the cache and if the two tags do not match, a cache miss is said to have occurred in the cache;

said restore tracking means comprising;

means for determining that a data retention time for the cache entry in said expired status and designating that data associated with the entry has an invalid status;

means for determining and designating that the data has a modified status; and

means for generating a refresh search request for data whose status is both invalid and modified;

said control logic means comprising search control logic means for detecting said search request and process a refresh search and a refresh interrupt, during which regular access to said directory is interrupted for the refresh search and the address space of the directory is searched until a directory entry associated with the data whose said status is both invalid and modified is located;

said control logic further comprising means for refreshing the data in the DRAM cache corresponding to a located directory entry and resetting the invalid status.

10. The restore tracking system of claim 1, wherein a periodic refresh of DRAM entries is eliminated.

11. The restore tracking system of claim 1, wherein said restore tracking system is coupled to a directory memory array and a cache.

12. The restore tracking system of claim 1, further comprising means for tracking when a memory location was last restored.

13. The restore tracking system of claim 1, wherein said restore tracking means comprises one of an analog and a discrete timing component for tracking said refresh status.

14. The restore tracking system of claim 13 wherein said timing component is a saturating N bit digital counter, having an input to controllably reset the counter.

15. The restore tracking system of claim 13, further comprising:

said timing component comprising an analog timing component wherein time is represented by charge collected on a capacitor.

16. The restore tracking system of claim 15, further comprising:

an external timer, coupled to said analog timing component, for periodically depositing charge onto the capacitor and causing a voltage across the capacitor to increase by a proportional amount until the capacitor accumulates enough charge so that the voltage crosses a predetermined threshold.

17. The restore tracking system of claim 13, wherein said analog timing component comprises a DRAM cell;

said DRAM cell coupled to a thresholding detecting device for determining the refresh status; and

a reset device which sets the DRAM cell to a known voltage.

18. The restore tracking system of claim 1, said restore tracking means further comprising:

a timer for monitoring a total time elapsed since said entry was last refreshed; and

timer reset logic for restarting said timer upon determining said entry has been restored by a naturally occurring read or write action to said DRAM.

19. The restore tracking system of claim 18, wherein said timer is an internal timing element, further comprising:

a restart input which when enabled will reset the timer to a start position;

a data retention output which when active indicates said entry has reached a maximum data retention time.

20. The restore tracking system of claim 18 wherein said internal timing element is connected to a system clock through at least one stage of timing logic, comprising:

a master digital clock derived off said system clock which produces a pulse only after an integral number of system clock cycles have occurred; and

a plurality of said digital timers, fed by said master digital clock, which counts in increments of master digital clock pulses.

21. The restore tracking system of claim 19, wherein said internal timing element is connected to an external clock which is dedicated to restore and wherein said internal timing element is one of an analog or digital timer.

22. The restore tracking system of claim 18, further comprising:

a directory memory array; and

a cache;

wherein said restore tracking system is coupled to the directory memory array and the cache;

said restore tracking means comprising means for monitoring a data retention time of blocks of memory indirectly by way of the directory memory array.

23. The restore tracking system of claim 1, further comprising:

a directory memory array coupled to said restore tracking means;

hit logic means, coupled to said directory memory array and to said restore tracking means, for generating a hit logic signal which indicates a directory hit or miss;

wherein the hit logic signal is used to determine whether said block of cells within the DRAM will be restored by one of a read or write operation.

24. The restore tracking system of claim 22 further comprising:

a directory memory array coupled to said restore tracking means;

status logic for forming a status signal for said restore tracking means by combining said data retention time with an output of status bits commonly used by the directory.

25. The restore tracking system of claim 24, wherein the status bits are selected from the group consisting of one or more of:

an invalid bit;

a valid bit;

a modified bit; and

an unmodified bit.

26. The restore tracking system of claim 22 wherein said restore tracking means are driven directly by decoded or partially decoded address bits of said directory.

27. The restore tracking system of claim 22, wherein decoded or partially decoded address bits of said directory feed logic, which performs “

AND”

or “

OR”

operations for one or more of restricting and broadening the address space covered by each restore tracking means, and following an address space transformation, the resultant signals feed said restore tracking means.

28. The restore tracking system of claim 1, further comprising means for refreshing only those entries that have been modified.

29. The restore tracking system of claim 1, wherein said restore tracking system is coupled to a directory memory array and a cache and wherein said DRAM is integrated in said cache, further comprising means for invalidating in the directory, data packets whose data will expire, but exist in duplicate within the memory hierarchy.

30. The restore tracking system of claim 1, wherein said control logic means further comprises:

search logic means for searching the cache directory to isolate an address having modified data and an expired data retention timer, so that the cache entry corresponding to said address may be refreshed.

42. The restore tracking system of claim 13, wherein said analog timing component comprises a DRAM cell;

said DRAM cell coupled to a thresholding detecting device for determining the refresh status; and

a reset device which sets the DRAM cell to a known voltage.

31. In a system including DRAM integrated within a cache memory, a restore tracking system, for reducing a number of refresh actions needed to maintain data in said DRAM, the restore tracking system comprising:

said DRAM including blocks of memory cells which can be refreshed by an external mechanism;

a restore tracking circuit devoted to each said block of memory cells for the purpose of tracking a total time elapsed since said block was last restored;

wherein said external mechanism comprises external means for triggering a refresh of said block if said restore tracking circuit of the said block reaches a maximum specified data retention time of said DRAM.

32. The restore tracking system of claim 31, wherein said external means for triggering a refresh, further comprises:

multiple said restore tracking circuits, each of which includes a dedicated timer;

each multiple restore tracking circuit comprising means for asserting a positive decoded refresh address signal once the dedicated timer has expired;

priority encode logic, coupled to said restore tracking circuits, for mapping one positive said decoded refresh address signal at a time to an encoded refresh address, and handling multiple requests over an extended period of memory cycles using a predetermined ordering, inconsequential to the restore process, wherein more than one said decoded refresh address signal may be positive at any given time; and

said priority encode logic comprising means for producing both;

said encoded refresh address, which is sent to the DRAM cache; and

a refresh request control signal, which directs said DRAM to process refresh of said encoded refresh address.

33. The restore tracking system of claim 31, further comprising:

said restore tracking circuit comprising a timer for tracking a time elapsed since a data entry has been refreshed;

OR logic, coupled to said restore tracking circuit, for generating a search request if the timer expires; and

said control logic comprising search control logic, coupled to said OR logic, for locating an address of the expired timer.

34. The restore tracking system of claim 31, further comprising:

a cache directory coupled to the restore tracking circuit;

search logic for searching the cache directory to isolate an address having modified data and an expired data retention timer, so that a cache entry corresponding to said address can be refreshed.

35. The restore tracking system of claim 31, wherein a periodic refresh of DRAM entries is eliminated.

36. The restore tracking system of claim 31, wherein said restore tracking system is coupled to a directory memory array and the cache.

37. The restore tracking system of claim 31, further comprising means for tracking when a memory location was last restored.

38. The restore tracking system of claim 31, wherein said restore tracking circuit comprises one of an analog and a discrete timing component for tracking one or more of said refresh status and said expired status.

39. The restore tracking system of claim 38 wherein said timing component is a saturating N bit digital counter, having an input to controllably reset the counter.

40. The restore tracking system of claim 38, further comprising:

said timing component comprising an analog timing component wherein time is represented by charge collected on a capacitor.

41. The restore tracking circuit of claim 40, further comprising:

an external timer, coupled to said analog timing component, for periodically depositing charge onto the capacitor and causing a voltage across the capacitor to increase by a proportional amount until the capacitor accumulates enough charge so that the voltage crosses a predetermined threshold.

43. The restore tracking circuit of claim 31, said restore tracking means further comprising:

a timer for monitoring a total time elapsed since said entry was last refreshed; and

timer reset logic for restarting said timer upon determining said entry has been restored by a naturally occurring read or write action to said DRAM.

44. The restore tracking circuit of claim 43, wherein said timer is an internal timing element, further comprising:

a restart input which when enabled will reset said timer to a start position;

a data retention output which when active indicates said entry has reached a maximum data retention time.

45. The restore tracking circuit of claim 43 wherein said internal timing element is connected to a system clock through at least one stage of timing logic, comprising:

a master digital clock derived off said system clock which produces a pulse only after an integral number of system clock cycles have occurred; and

a plurality of said digital timers, fed by said master digital clock, which counts in increments of master digital clock pulses.

46. The restore tracking circuit of claim 44, wherein said internal timing element is connected to an external clock which is dedicated to restore and wherein said internal timing element is one of an analog or digital timer.

47. A method for refreshing a DRAM, comprising the step of selectively refreshing only a subset of a DRAM data that has not already been refreshed by a read or write action;

wherein a refresh is performed without requiring a periodic interrupt to refresh the DRAM.

48. The method of claim 47, wherein said DRAM comprises a DRAM cache, further comprising the steps of:

searching a cache directory to isolate an address having modified data and an expired data retention timer;

refreshing a cache entry corresponding to said address, in response to said searching step.

49. A method for searching a cache directory, so that a cache entry in a DRAM cache corresponding to a directory address in said cache directory may be refreshed, comprising the steps of:

(a) identifying a directory address associated with data having a status of modified and invalid;

wherein an invalid status is associated with an expired data retention timer;

(b) initiating a refresh search of the cache directory and interrupting regular access to the cache directory, in response to said identifying step;

(c) searching cache addresses in the cache directory and reading said invalid and modified status of an associated directory entry;

(d) if both a modified status bit and an invalid status bit of the directory entry are true, then identifying a cache address and proceeding to step (e), else returning to said step (b);

(e) sending the refresh address to the cache so the cache entry may be restored; and

(f) resetting the invalid bit to zero.

50. A method for reducing a number of refresh actions needed to maintain data entries in a DRAM, comprising the steps of:

recording and updating a refresh status of one or more of said data entries in said DRAM; and

refreshing said one or more of said data entries having an expired status.

51. The method of claim 50, further comprising the steps of:

tracking a time elapsed since a data entry has been refreshed;

determining that a data retention time for the data entry has expired; and

asserting a positive decoded refresh address signal for an expired data entry; and

mapping said positive decoded refresh address signal to an encoded refresh address.

52. The method of claim 50, wherein said DRAM is integrated within said cache memory.

53. The method of claim 50, wherein said DRAM includes blocks of memory cells which are refreshed by an external means, said method further comprising the steps of:

a plurality of restore tracking circuits, each devoted to a block of memory cells for tracking a time elapsed since said block was last restored, and specifying a maximum data retention time of said DRAM; and

triggering a refresh of said block if said block reaches said maximum data retention time.

54. The method of claim 50, wherein said DRAM is coupled to said restore tracking circuit, said DRAM including blocks of memory cells which are refreshed by naturally occurring read and write actions, said method further comprising the steps of:

monitoring a total time elapsed since a block of memory was last refreshed;

determining said block has been restored by said naturally occurring read or write actions to said DRAM; and

restarting said monitoring, in response to said step of determining said block of cells has been restored by said naturally occurring read or write actions to said DRAM.

55. The method of claim 50, further comprising the steps of:

tracking a time elapsed since a data entry has been refreshed;

determining that a data retention time for the data entry has expired; and

generating a search request if the retention time for the data entry has expired; and

locating an address of an expired data entry.

56. The method of claim 50, wherein a periodic refresh of DRAM entries is eliminated.

57. The method of claim 50, wherein said restore tracking system is coupled to a directory memory array and a cache.

58. The method of claim 50, further comprising the step of tracking when a memory location was last restored.

59. The method of claim 50, further comprising the step of providing one of an analog and a discrete timing component for tracking one or more of said refresh status and said expired status.

60. The method of claim 59, wherein said timing component comprises an analog timing component, the method further comprising the step of:

collecting charge on the capacitor, wherein time is represented by an amount of charge collected on the capacitor.

61. The method of claim 51, further comprising the step of:

an external timer periodically depositing charge onto the capacitor causing a voltage across the capacitor to increase by a proportional amount until the capacitor accumulates enough charge so that the voltage crosses a predetermined threshold.

62. The method of claim 59, wherein said analog timing component comprises a DRAM cell;

said DRAM cell coupled to a thresholding detecting device for determining the refresh status; and

a reset device which sets the DRAM cell to a known voltage.

63. The method of claim 50, further comprising the steps of:

a timer monitoring a total time elapsed since said entry was last refreshed;

determining said entry has been restored by a naturally occurring read or write action to said DRAM; and

restarting said timer, in response to said determining step.

64. The method of claim 63, wherein said timer is an internal timing element selected from a group consisting of:

an analog timer;

or a digital timer.

65. The method of claim 50, further comprising the step of refreshing only those entries that have been modified.

66. The method of claim 50, wherein said DRAM is integrated within a cache memory, further comprising the step of searching a cache directory to isolate an address having modified data and an expired data retention timer, so that a cache entry corresponding to said address may be refreshed.

67. In a memory hierarchy including DRAM integrated within a store-through cache memory, a restore tracking system for reducing a number of refresh actions needed to maintain data in said DRAM, the restore tracking system comprising:

said DRAM cache subdivided into blocks of memory cells storing data at a first level of the hierarchy;

a directory for said DRAM cache;

a second level of the hierarchy including a superset of data stored within said DRAM cache;

a restore tracking circuit devoted to each said block of memory cells, said restore tracking circuit comprising;

a timer for tracking a total time elapsed since a block of memory was last restored;

an invalid status bit coupled to the timer and to the directory for a directory status of said block of memory;

wherein if said timer for said block expires, said invalid bit is set so that a subsequent request for said block will produce a miss in the directory and cause said block to be fetched from said next level of memory hierarchy.

68. The restore tracking circuit of claim 67, wherein said DRAM is coupled to said restore tracking means, said DRAM including blocks of memory cells which are refreshed by naturally occurring read and write actions, said restore tracking circuit further comprising:

timer reset logic, coupled to the timer, for restarting said timer upon determining said block of cells has been restored by said naturally occurring read or write actions to said DRAM.

69. The restore tracking system of claim 67, wherein the timer is selected from a group consisting of an analog timing component or a discrete timing component.

70. The restore tracking system of claim 69 wherein the timer is a saturating N bit digital counter, having an input to controllably reset the counter.

71. The restore tracking system of claim 69, further comprising:

the analog timing component wherein time is represented by charge collected on a capacitor.

72. The restore tracking system of claim 71, further comprising:

an external timer, coupled to said analog timing component, for periodically depositing charge onto the capacitor and causing a voltage across the capacitor to increase by a proportional amount until the capacitor accumulates enough charge so that the voltage crosses a predetermined threshold.

73. The restore tracking system of claim 69, wherein said analog timing component comprises a DRAM cell;

said DRAM cell coupled to a thresholding detecting device for determining the refresh status; and

a reset device which sets the DRAM cell to a known voltage.

79. The method of claim 72, further comprising the step of:

an external timer periodically depositing charge onto the capacitor and causing a voltage across the capacitor to increase by a proportional amount; and

detecting that the capacitor has accumulated enough charge so that the voltage crosses a predetermined threshold.

74. A method for reducing a number of refresh actions needed to maintain data entries in a DRAM, comprising:

recording and updating a refresh status of one or more of said data entries in said DRAM; and

invalidating said one or more of said data entries having an expired status.

75. The method of claim 74, wherein said DRAM is coupled to said restore tracking means, said DRAM including blocks of memory cells which are refreshed by naturally occurring read and write actions, said method further comprising the step of:

restarting a timer upon determining said block of cells has been restored by said naturally occurring read or write actions to said DRAM.

76. The method of claim 74, wherein the timer is selected from a group consisting of an analog timing component or a discrete timing component.

77. The method of claim 76 wherein the timer is a saturating N bit digital counter, having an input to controllably reset the counter.

78. The method of claim 76, further comprising the step of:

the analog timing component wherein time is represented by charge collected on a capacitor.

80. The method of claim 76, wherein said analog timing component comprises a DRAM cell coupled to a threshold detecting device, further comprising the step of:

the threshold detecting device detecting the refresh status; and

setting the DRAM cell to a known voltage, in response to said determining step.